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1. general description the lpc5411x are arm cortex-m4 based microcontrollers for embedded applications. these devices include an arm cortex-m0+ coprocessor, up to 192 kb of on-chip sram, up to 256 kb on-chip flash, full-speed usb device interface with crystal-less operation, a dmic subsystem with pdm microphone interfac e and i2s, five general-purpose timers, one sctimer/pwm, one rtc/alarm timer, one 24-bit multi-rate timer (mrt), a windowed watchdog timer (wwdt), eight flex ible serial communication peripherals (each of which can be a usart, spi, or i 2 c interface), and one 12-bit 5.0 msamples/sec adc, and a temperature sensor. the arm cortex-m4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a hi gh level of support block integration. the arm cortex-m4 cpu incorporates a 3-stage pi peline, uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. the arm cortex-m4 supports single-cycle digital si gnal processing and simd instructions. a hardware floating-point unit is integrated in the core. the arm cortex-m0+ coprocessor is an energy-efficient and easy-to-use 32-bit core which is code and tool-compatible with the cortex-m4 core. the cortex-m0+ coprocessor offers up to 100 mhz performance with a simple instruction set and reduced code size. 2. features and benefits ? dual processor cores: arm cortex-m4 and arm cortex-m0+. both cores operate up to a maximum frequency of 100 mhz. ? arm cortex-m4 core (version r0p1): ? arm cortex-m4 processor, running at a frequency of up to 100 mhz. ? floating point unit (fpu) and memory protection unit (mpu). ? arm cortex-m4 built-in nested vector ed interrupt controller (nvic). ? non-maskable interrupt (nmi) in put with a selection of sources. ? serial wire debug (swd) with six instruct ion breakpoints, two literal comparators, and four watch points. includes seri al wire output for enhanced debug capabilities. ? system tick timer. lpc5411x 32-bit arm cortex-m4/m0+ mcu; 192 kb sram; 256 kb flash, crystal-less usb operation, dmic subsystem, flexcomm interface, 32-bit counter/ time rs, sctimer/pwm, 12-bit 5.0 msamples/sec adc, temperature sensor rev. 2.1 ? 9 may 2018 product data sheet
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 2 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ? arm cortex-m0+ core ? arm cortex-m0+ processor, running at a frequency of up to 100 mhz (uses the same clock as cortex-m4) with a single-cyc le multiplier and a fa st single-cycle i/o port. ? arm cortex-m0+ built-in nested vectored interrupt controller (nvic). ? non-maskable interrupt (nmi) in put with a selection of sources. ? serial wire debug with four breakpoints and two watch points. ? system tick timer. ? on-chip memory: ? up to 256 kb on-chip flash program memory with flash accelerator and 256 byte page erase and write. ? up to 192 kb total sram consisting of 160 kb contiguous main sram and an additional 32 kb sram on the i&d buses. ? rom api support: ? flash in-application programming (iap) and in-system programming (isp). ? rom-based usb drivers (hid, cdc, msc, and dfu). flash updates via usb is supported. ? supports booting from valid user code in flash, usart, spi, and i 2 c. ? legacy, single, and dual image boot. ? serial interfaces: ? flexcomm interface contains eight serial peripherals. each can be selected by software to be a usart, spi, or i 2 c interface. two flexcomm interfaces also include an i 2 s interface. each flexcomm interfac e includes a fifo that supports usart, spi, and i 2 s if supported by that flexcomm interface. a variety of clocking options are available to each flexcomm in terface and include a shared fractional baud-rate generator. ? i 2 c-bus interfaces support fast-mode and fast-mode plus with data rates of up to 1mbit/s and with multiple address recognition and monitor mode. two sets of true i 2 c pads also support high speed mode (3.4 mbit/s) as a slave. ? usb 2.0 full-speed device controller with on-chip phy and dedicated dma controller supporting crystal-less operation in device mode using software library. see technical note tn00031 for more details. ? digital peripherals: ? dma controller with 20 channels and 20 programmable triggers, able to access all memories and dma-capable peripherals. ? up to 48 general-purpose input/outpu t (gpio) pins. most gpios have configurable pull-up/pull-down resistors, programmable open-drain mode, and input inverter. ? gpio registers are located on the ahb for fast access. ? up to eight gpios can be selected as pin interrupts (pint), triggered by rising, falling or both input edges. ? two gpio grouped interrupts (gint) enable an interrupt based on a logical (and/or) combination of input states. ? crc engine.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 3 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ? analog peripherals: ? 12-bit adc with 12 input channels and with multiple internal and external trigger inputs and sample rates of up to 5.0 msamples/sec. the adc supports two independent conversion sequences. ? integrated temperature sensor connected to the adc. ? dmic subsystem including a dual-channel pdm microphone interface, flexible decimators, 16 entry fifos, optional dc locking, hardware voice activity detection, and the option to stream the processed output data to i 2 s. ? timers: ? five 32-bit standard general purpose timers /counters, four of which support up to four capture inputs and four compare outputs, pwm mode, and external count input. specific timer events can be selected to generate dma requests. the fifth timer does not have external pin connections and may be used for internal timing operations. ? one sctimer/pwm with eight input and eigh t output functions (including capture and match). inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. inte rnally, the sctimer/pwm supports ten captures/matches, ten events, and ten states. ? 32-bit real-time clock (rtc) with 1 s reso lution running in the always-on power domain. a timer in the rtc can be used for wake-up from all low power modes including deep power-down, with 1 ms resolution. ? multiple-channel multi-rate 24-bit timer (mrt) for repetitive interrupt generation at up to four programmable, fixed rates. ? windowed watchdog timer (wwdt). ? clock generation: ? 12 mhz internal free runni ng oscillator (fro). this oscillator provides a selectable 48 mhz or 96 mhz output, and a 12 mhz output (divided down from the selected higher frequency) that can be used as a system clock. the fro is trimmed to ? 1 % accuracy over the entire voltage and temperature range. ? external clock input for clock frequencies of up to 25 mhz. ? watchdog oscillator (wdtosc) with a fr equency range of 6 khz to 1.5 mhz. ? 32.768 khz low-power rtc oscillator. ? system pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency external clock. may be run from the internal fro 12 mhz output, the external clock inpu t clkin, or the rtc oscillator. ? clock output function with divider. ? frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal. ? power control: ? programmable pmu (power management un it) to minimize power consumption and to match requirements at different performance levels. ? reduced power modes: sleep, deep-sleep, and deep power-down. ? wake-up from deep-sleep modes due to activity on the usart, spi, and i2c peripherals when operating as slaves.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 4 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ? the micro-tick timer running from the watchdog oscillato r can be used to wake-up the device from any reduced power modes. ? power-on reset (por). ? brown-out detect (bod) with separate th resholds for interrup t and forced reset. ? single power supply 1.62 v to 3.6 v. ? jtag boundary scan supported. ? 128 bit unique device serial number for identification. ? operating temperature range ? 40 c to +105 c. ? available as wlcsp49 and lqfp64 packages.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 5 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 3. ordering information 3.1 ordering options 4. marking table 1. ordering information type number package name description version lpc54113j256uk49 wlcsp49 wafer level chip-size package; 49 (7 x 7) bumps; 3.436 x 3.436 x 0.525 mm - lpc54114j256uk49 wlcsp49 wafer level chip-size package; 49 (7 x 7) bumps; 3.436 x 3.436 x 0.525 mm - LPC54113J128BD64 lqfp64 plastic low prof ile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc54113j256bd64 lqfp64 plastic low prof ile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc54114j256bd64 lqfp64 plastic low prof ile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 table 2. ordering options type number flash in kb sram in kb cortex-m4 with fpu cortex-m0+ usb fs gpio sramx sram0 sram1 sram2 total lpc54113j256uk49 256 32 64 64 32 192 1 0 1 37 lpc54114j256uk49 256 32 64 64 32 192 1 1 1 37 LPC54113J128BD64 128 32 64 - - 96 1 0 1 48 lpc54113j256bd64 256 32 64 64 32 192 1 0 1 48 lpc54114j256bd64 256 32 64 64 32 192 1 1 1 48 fig 1. lqfp64 package marking fig 2. wlcsp49 package marking 1 n terminal 1 index area aaa-011231 aaa-015675 terminal 1 index area
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 6 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller the lpc5411x lqfp64 package has the following top-side marking: ? first line: lpc5411xjyyy ? x: 4 = dual core (m4, m0+) ? x: 3 = single core (m4) ? yyy: flash size ? second line: bd64 ? third line: xxxxxxxxxxxx ? fourth line: xxxyywwx[r]x ? yyww: date code with yy = year and ww = week. ? xr = boot code version and device revision. the lpc5411x wlcsp49 package has the following top-side marking: ? first line: lpc5411x ? x: 4 = dual core (m4, m0+) ? x: 3 = single core (m4) ? second line: jxxxuk49 ? xxx: flash size ? third line: xxxxxxxx ? fourth line: xxxyyww ? yyww: date code with yy = year and ww = week. ? fifth line: xxxxx ? sixth line: nxp x[r]x ? xr = boot code version and device revision. table 3. device revision table revision description ?0a? initial device revision with boot code version 18.0.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 7 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 5. block diagram each flexcomm interface includes usart, spi, and i 2 c functions. flexcomm interfaces 6 and 7 each also provide an i2s function. grey-shaded blocks indicate peripherals that provide dma requests or are otherwise able to trigger dma transfers fig 3. lpc5411x block diagram aaa-022099 usb fs device controller arm cortex m0+ flash accelerator flash 256 kb arm cortex m4 fpu mpu debug interface 2 32-bit timer (timer 3, 4) 2 32-bit timer (timer 0, 1) gpio pin interrupts multilayer ahb matrix i/o configuration gpio group interrupts 0 and 1 peripheral input muxes multi-rate timer frequency measurement unit pmu registers 32-bit timer (timer 2) flash registers flexcomm interfaces 5 through 7 (1) dmic subsystem registers adc: 5 ms/s, 12 bit, 12 ch. temperature sensor gpio sctimer/pwm fractional rate generator system functions: clocking, reset, power, flash, etc. serial wire debug usb bus jtag boundary scan clkin clkout reset i-code d-code system system dma controller clock generation, power control, and other system functions power-on-reset brownout detect internal oscillator system pll boot and driver rom 32 kb sramx 32 kb sram0 64 kb mailbox dma registers usb registers async apb bridge apb bridge 0 real time clock, alarm and wakeup 32.768 khz oscillator watchdog oscillator windowed watchdog micro tick timer apb bridge 1 crc engine sram1 64 kb sram2 32 kb flexcomm interfaces 0 through 4 (1)
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 8 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 6. pinning information 6.1 pinning fig 4. wlcsp49 pin configuration ball a1 (pin #1) index area a b c d e f g 7 6 5 4 3 2 1 aaa-015470
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 9 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller fig 5. lqfp64 pin configuration lpc5411x 49 pio0_14 32 pio0_1 50 pio0_15 31 pio0_0 51 pio1_12 30 pio1_10 52 swclk/ pio0_16 29 pio1_9 53 swdio/ pio0_17 28 pio1_8 54 pio1_13 27 pio1_7 55 vss 26 pio1_6 56 vdd 25 vss 57 pio1_14 24 vdd 58 pio0_18 23 vdda 59 pio0_19 22 vrefp 60 pio0_20 21 vrefn 61 pio0_21 20 vssa 62 pio1_15 19 pio1_5 63 pio0_22 18 pio1_4 64 reset 17 pio1_3 1 pio0_23 48 pio0_13 2 pio0_24 47 pio0_12 3 pio0_25 46 pio0_11 4 pio0_26 45 pio0_10 5 usb_dp 44 pio0_9 6 usb_dm 43 pio0_8 7 pio1_16 42 pio1_11 8 vdd 41 pio0_7 9 vss 40 pio0_6 10 pio1_17 39 pio0_5 11 pio0_29 38 pio0_4 12 pio0_30 37 pio0_3 13 pio0_31 36 pio0_2 14 pio1_0 35 rtcxout 15 pio1_1 34 vdd 16 pio1_2 33 rtcxin aaa-019386
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 10 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 6.2 pin description on the lpc5411x, digital pins are grouped into two ports. each digital pin may support up to four different digital functions and one analog function, including general purpose i/o (gpio). table 4. pin description symbol 49-pin 64-pin reset state [1] type description pio0_0 a6 31 [2] pu i/o pio0_0 ? general-purpose digital input/output pin. remark: in isp mode, this pin is set to the flexcomm interface 0 usart rxd function. i/o fc0_rxd_sda_mosi ? flexcomm interface 0: usart rxd, i2c sda, spi mosi. i/o fc3_cts_sda_ssel0 ? flexcomm interface 3: us art cts, i2c sda, spi ssel0. i ctimer0_cap0 ? 32-bit ctimer0 capture input 0. r ? reserved. o sct0_out3 ? sct0 output 3. pwm output 3. pio0_1 b6 32 [2] pu i/o pio0_1 ? general-purpose digital input/output pin. remark: in isp mode, this pin is set to the flexcomm interface 0 usart txd function. i/o fc0_txd_scl_miso ? flexcomm interface 0: usart txd, i2c scl, spi miso. i/o fc3_rts_scl_ssel1 ? flexcomm interface 3: u sart rts, i2c scl, spi ssel1. i ctimer0_cap1 ? 32-bit ctimer0 capture input 1. r ? reserved. o sct0_out1 ? sct0 output 1. pwm output 1. pio0_2 - 36 [2] pu i/o pio0_2 ? general-purpose digital input/output pin. i/o fc0_cts_sda_ssel0 ? flexcomm interface 0: us art cts, i2c sda, spi ssel0. i/o fc3_ssel3 ? flexcomm interface 3: spi ssel3. i ctimer2_cap1 ? 32-bit ctimer2 capture input 1. pio0_3 - 37 [2] pu i/o pio0_3 ? general-purpose digital input/output pin. i/o fc0_rts_scl_ssel1 ? flexcomm interface 0: u sart rts, i2c scl, spi ssel1. i/o fc2_ssel2 ? flexcomm interface 2: spi ssel2. o ctimer1_mat3 ? 32-bit ctimer1 match output 3. pio0_4 c7 38 [2] pu i/o pio0_4 ? general-purpose digital input/output pin. remark: the state of this pin at reset in conjunction with pio0_31 and pio1_6 will determine the boot source for the part or if isp handler is invoked. see the boot process chapter in um10914 for more details. i/o fc0_sck ? flexcomm interface 0: usart or spi clock. i/o fc3_ssel2 ? flexcomm interface 3: spi ssel2. i ctimer0_cap2 ? 32-bit ctimer0 capture input 2.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 11 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller pio0_5 c6 39 [2] pu i/o pio0_5 ? general-purpose digital input/output pin. i/o fc6_rxd_sda_mosi_data ? flexcomm interface 6: usart rxd, i2c sda, spi mosi, i2s data. o sct0_out6 ? sct0 output 6. pwm output 6. o ctimer0_mat0 ? 32-bit ctimer0 match output 0. pio0_6 d7 40 [2] pu i/o pio0_6 ? general-purpose digital input/output pin. i/o fc6_txd_scl_miso_ws ? flexcomm interface 6: usart txd, i2c scl, spi miso, i2s ws. r ? reserved. o ctimer0_mat1 ? 32-bit ctimer0 match output 1. r ? reserved. i utick_cap0 ? micro-tick timer capture input 0. pio0_7 d6 41 [2] pu i/o pio0_7 ? general-purpose digital input/output pin. i/o fc6_sck ? flexcomm interface 6: usart, spi, or i2s clock. o sct0_out0 ? sct0 output 0. pwm output 0. o ctimer0_mat2 ? 32-bit ctimer0 match output 2. r ? reserved. i ctimer0_cap2 ? 32-bit ctimer0 capture input 2. pio0_8 d5 43 [2] pu i/o pio0_8 ? general-purpose digital input/output pin. i/o fc2_rxd_sda_mosi ? flexcomm interface 2: usart rxd, i2c sda, spi mosi. o sct0_out1 ? sct0 output 1. pwm output 1. o ctimer0_mat3 ? 32-bit ctimer0 match output 3. pio0_9 e7 44 [2] pu i/o pio0_9 ? general-purpose digital input/output pin. i/o fc2_txd_scl_miso ? flexcomm interface 2: usart txd, i2c scl, spi miso. o sct0_out2 ? sct0 output 2. pwm output 2. i ctimer3_cap0 ? 32-bit ctimer3 capture input 0. r ? reserved. i/o fc3_cts_sda_ssel0 ? flexcomm interface 3: us art cts, i2c sda, spi ssel0. pio0_10 e6 45 [2] pu i/o pio0_10 ? general-purpose digital input/output pin. i/o fc2_sck ? flexcomm interface 2: usart or spi clock. o sct0_out3 ? sct0 output 3. pwm output 3. o ctimer3_mat0 ? 32-bit ctimer3 match output 0. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 12 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller pio0_11 e5 46 [2] pu i/o pio0_11 ? general-purpose digital in put/output pin. in isp mode, this pin is set to the flexcomm 3 spi sck function. i/o fc3_sck ? flexcomm interface 3: usart or spi clock. i/o fc6_rxd_sda_mosi_data ? flexcomm interface 6: usart rxd, i2c sda, spi mosi, i2s data. o ctimer2_mat1 ? 32-bit ctimer2 match output 1. pio0_12 f7 47 [2] pu i/o pio0_12 ? general-purpose digital input/output pin. in isp mode, this pin is set to the flexcomm 3 spi mosi function. i/o fc3_rxd_sda_mosi ? flexcomm interface 3: usart rxd, i2c sda, spi mosi. i/o fc6_txd_scl_miso_ws ? flexcomm interface 6: usart txd, i2c scl, spi miso, i2s ws. o ctimer2_mat3 ? 32-bit ctimer2 match output 3. pio0_13 g7 48 [2] pu i/o pio0_13 ? general-purpose digital input/output pin. in isp mode, this pin is set to the flexcomm 3 spi miso function. i/o fc3_txd_scl_miso ? flexcomm interface 3: usart txd, i2c scl, spi miso. o sct0_out4 ? sct0 output 4. pwm output 4. o ctimer2_mat0 ? 32-bit ctimer2 match output 0. pio0_14/ tck f6 49 [2] pu i/o pio0_14 ? general-purpose digital input/outpu t pin. in boundary scan mode: tck (test clock in). in isp mode, this pin is set to the flexcomm 3 spi sseln0 function. i/o fc3_cts_sda_ssel0 ? flexcomm interface 3: us art cts, i2c sda, spi ssel0. o sct0_out5 ? sct0 output 5. pwm output 5. o ctimer2_mat1 ? 32-bit ctimer2 match output 1. r ? reserved. i/o fc1_sck ? flexcomm interface 1: usart or spi clock. pio0_15/ tdo g6 50 [2] pu i/o pio0_15 ? general-purpose digital input/outpu t pin. in boundary scan mode: tdo (test data out). i/o fc3_rts_scl_ssel1 ? flexcomm interface 3: u sart rts, i2c scl, spi ssel1. i/o swo ? serial wire trace output. o ctimer2_mat2 ? 32-bit ctimer2 match output 2. r ? reserved. i/o fc4_sck ? flexcomm interface 4: usart or spi clock. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 13 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller swclk/ pio0_16 f5 52 [2] pu i/o pio0_16 ? general-purpose digital input/output pin. i/o fc3_ssel2 ? flexcomm interface 3: spi ssel2. i/o fc6_cts_sda_ssel0 ? flexcomm interface 6: us art cts, i2c sda, spi ssel0. o ctimer3_mat1 ? 32-bit ctimer3 match output 1. r ? reserved. i/o swclk ? serial wire clock. jtag test clock. this is the default function after booting. r ? reserved. swdio/ pio0_17 g5 53 [2] pu i/o pio0_17 ? general-purpose digital input/output pin. i/o fc3_ssel3 ? flexcomm interface 3: spi ssel3. i/o fc6_rts_scl_ssel1 ? flexcomm interface 6: u sart rts, i2c scl, spi ssel1. o ctimer3_mat2 ? 32-bit ctimer3 match output 2. r ? reserved. i/o swdio ? serial wire debug i/o. this is the default function after booting. pio0_18/ trst g4 58 [2] pu i/o pio0_18 ? general-purpose digital input/output pin. in boundary scan mode: trst (test reset). i/o fc5_txd_scl_miso ? flexcomm interface 5: usart txd, i2c scl, spi miso. o sct0_out0 ? sct0 output 0. pwm output 0. o ctimer0_mat0 ? 32-bit ctimer0 match output 0. pio0_19/ tdi g3 59 [2] pu i/o pio0_19 ? general-purpose digital input/outpu t pin. in boundary scan mode: tdi (test data in). i/o fc5_sck ? flexcomm interface 5: usart or spi clock. o sct0_out1 ? sct0 output 1. pwm output 1. o ctimer0_mat1 ? 32-bit ctimer0 match output 1. pio0_20/ tms f3 60 [2] pu i/o pio0_20 ? general-purpose digital input/outpu t pin. in boundary scan mode: tms (test mode select). i/o fc5_rxd_sda_mosi ? flexcomm interface 5: usart rxd, i2c sda, spi mosi. i/o fc0_sck ? flexcomm interface 0: usart or spi clock. i ctimer3_cap0 ? 32-bit ctimer3 capture input 0. pio0_21 e3 61 [2] pu i/o pio0_21 ? general-purpose digital input/output pin. o clkout ? clock output. i/o fc0_txd_scl_miso ? flexcomm interface 0: usart txd, i2c scl, spi miso. o ctimer3_mat0 ? 32-bit ctimer3 match output 0. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 14 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller pio0_22 g2 63 [2] pu i/o pio0_22 ? general-purpose digital input/output pin. i clkin ? clock input. i/o fc0_rxd_sda_mosi ? flexcomm interface 0: usart rxd, i2c sda, spi mosi. o ctimer3_mat3 ? 32-bit ctimer3 match output 3. pio0_23 f2 1 [3] zi/o pio0_23 ? general-purpose digital input/output pin. in isp mode, this pin is set to the flexcomm 1 i2c scl function. i/o fc1_rts_scl_ssel1 ? flexcomm interface 1: u sart cts, i2c scl, spi ssel1. r ? reserved. i ctimer0_cap0 ? 32-bit ctimer0 capture input 0. r ? reserved. i utick_cap1 ? micro-tick timer capture input 1. pio0_24 f1 2 [3] zi/o pio0_24 ? general-purpose digital input/output pin. in isp mode, this pin is set to the flexcomm 1 i2c sda function. i/o fc1_cts_sda_ssel0 ? flexcomm interface 1: us art cts, i2c sda, spi ssel0. r ? reserved. i ctimer0_cap1 ? 32-bit ctimer0 capture input 1. r ? reserved. o ctimer0_mat0 ? 32-bit ctimer0 match output 0. pio0_25 e2 3 [3] zi/o pio0_25 ? general-purpose digital input/output pin. i/o fc4_rts_scl_ssel1 ? flexcomm interface 4: u sart cts, i2c scl, spi ssel1. i/o fc6_cts_sda_ssel0 ? flexcomm interface 6: us art cts, i2c sda, spi ssel0. i ctimer0_cap2 ? 32-bit ctimer0 capture input 2. r ? reserved. i ctimer1_cap1 ? 32-bit ctimer1 capture input 1. pio0_26 e1 4 [3] zi/o pio0_26 ? general-purpose digital input/output pin. i/o fc4_cts_sda_ssel0 ? flexcomm interface 4: us art cts, i2c sda, spi ssel0. r ? reserved. i ctimer0_cap3 ? 32-bit ctimer0 capture input 3. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 15 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller pio0_29/ adc0_0 d3 11 [4] pu i/o; ai pio0_29/adc0_0 ? general-purpose digital input/output pin. adc input channel 0 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc1_rxd_sda_mosi ? flexcomm interface 1: usart rxd, i2c sda, spi mosi. o sct0_out2 ? sct0 output 2. pwm output 2. o ctimer0_mat3 ? 32-bit ctimer0 match output 3. r ? reserved. i ctimer0_cap1 ? 32-bit ctimer0 capture input 1. r ? reserved. o ctimer0_mat1 ? 32-bit ctimer0 match output 1. pio0_30/ adc0_1 c1 12 [4] pu i/o; ai pio0_30/adc0_1 ? general-purpose digital input/output pin. adc input channel 1 if the digimode bit is set to 0 in the iocon register for this pin. i/o fc1_txd_scl_miso ? flexcomm interface 1: usart txd, i2c scl, spi miso. o sct0_out3 ? sct0 output 3. pwm output 3. o ctimer0_mat2 ? 32-bit ctimer0 match output 2. r ? reserved. i ctimer0_cap2 ? 32-bit ctimer0 capture input 2. pio0_31/ adc0_2 c2 13 [4] pu i/o; ai pio0_31/adc0_2 ? general-purpose digital input/output pin. adc input channel 2 if the digimode bit is set to 0 in the iocon register for this pin. remark: this pin is also used to invoke isp mode after device reset. secondary selection of boot source for isp mode al so uses pio0_4 and pio1_6. see the boot process chapter in um10914 for more details. o pdm0_clk ? clock for pdm interface 0, for digital microphone. i/o fc2_cts_sda_ssel0 ? flexcomm interface 2: us art cts, i2c sda, spi ssel0. i ctimer2_cap2 ? 32-bit ctimer2 capture input 2. r ? reserved. i ctimer0_cap3 ? 32-bit ctimer0 capture input 3. o ctimer0_mat3 ? 32-bit ctimer0 match output 3. pio1_0/ adc0_3 c3 14 [4] pu i/o; ai pio1_0/adc0_3 ? general-purpose digital input/outpu t pin. adc input channel 3 if the digimode bit is set to 0 in the iocon register for this pin. i pdm0_data ? data for pdm interface 0, digital microphone input. i/o fc2_rts_scl_ssel1 ? flexcomm interface 2: u sart rts, i2c scl, spi ssel1. o ctimer3_mat1 ? 32-bit ctimer3 match output 1. r ? reserved. i ctimer0_cap0 ? 32-bit ctimer0 capture input 0. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 16 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller pio1_1/ adc0_4 b1 15 [4] pu i/o; ai pio1_1/adc0_4 ? general-purpose digital input/outpu t pin. adc input channel 4 if the digimode bit is set to 0 in the iocon register for this pin. r ? reserved. i/o swo ? serial wire trace output. o sct0_out4 ? sct0 output 4. pwm output 4. i/o fc5_ssel2 ? flexcomm interface 5: spi ssel2. i/o fc4_txd_scl_miso ? flexcomm interface 4: usart txd, i2c scl, spi miso. pio1_2/ adc0_5 a1 16 [4] pu i/o; ai pio1_2/adc0_5 ? general-purpose digital input/outpu t pin. adc input channel 5 if the digimode bit is set to 0 in the iocon register for this pin. i/o mclk ? mclk input or output for i2s and/or digital microphone. i/o fc7_ssel3 ? flexcomm interface 7: spi ssel3. o sct0_out5 ? sct0 output 5. pwm output 5. i/o fc5_ssel3 ? flexcomm interface 5: spi ssel3. i/o fc4_rxd_sda_mosi ? flexcomm interface 4: usart rxd, i2c sda, spi mosi. pio1_3/ adc0_6 b2 17 [4] pu i/o; ai pio1_3/adc0_6 ? general-purpose digital input/outpu t pin. adc input channel 6 if the digimode bit is set to 0 in the iocon register for this pin. r ? reserved. i/o fc7_ssel2 ? flexcomm interface 7: spi ssel2. o sct0_out6 ? sct0 output 6. pwm output 6. r ? reserved. i/o fc3_sck ? flexcomm interface 3: usart or spi clock. i ctimer0_cap1 ? 32-bit ctimer0 capture input 1. o usb_up_led ? usb port 2 goodlink led indicator. it is low when the device is configured (non-control endpoints enabled). it is high when the device is not configured or during global suspend. pio1_4/ adc0_7 a2 18 [4] pu i/o; ai pio1_4/adc0_7 ? general-purpose digital input/outpu t pin. adc input channel 7 if the digimode bit is set to 0 in the iocon register for this pin. o pdm1_clk ? clock for pdm interface 1, for digital microphone. i/o fc7_rts_scl_ssel1 ? flexcomm interface 7: u sart rts, i2c scl, spi ssel1. o sct0_out7 ? sct0 output 7. pwm output 7. r ? reserved. i/o fc3_txd_scl_miso ? flexcomm interface 3: usart txd, i2c scl, spi miso. o ctimer0_mat1 ? 32-bit ctimer0 match output 1. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 17 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller pio1_5/ adc0_8 b3 19 [4] pu i/o; ai pio1_5/adc0_8 ? general-purpose digital input/outpu t pin. adc input channel 8 if the digimode bit is set to 0 in the iocon register for this pin. i pdm1_data ? data for pdm interface 1, digital microphone input. also pdm clock input in bypass mode. i/o fc7_cts_sda_ssel0 ? flexcomm interface 7: us art cts, i2c sda, spi ssel0. i ctimer1_cap0 ? 32-bit ctimer1 capture input 0. r ? reserved. o ctimer1_mat3 ? 32-bit ctimer1 match output 3. r ? reserved. o usb_frame ? usb start-of-frame signal derived from host signaling. pio1_6/ adc0_9 a5 26 [4] pu i/o; ai pio1_6/adc0_9 ? general-purpose digital input/outpu t pin. adc input channel 9 if the digimode bit is set to 0 in the iocon register for this pin. remark: this pin is also used as part of seco ndary selection of boot source for isp mode after device reset, in connection wi th pio0_31 and pio0_4. see the boot process chapter in um10914 for more details. r ? reserved. i/o fc7_sck ? flexcomm interface 7: usart, spi, or i2s clock. i ctimer1_cap2 ? 32-bit ctimer1 capture input 2. r ? reserved. o ctimer1_mat2 ? 32-bit ctimer1 match output 2. r ? reserved. i usb_vbus ? monitors the presence of usb bus power. this signal must be high for usb reset to occur. pio1_7/ adc0_10 b5 27 [4] pu i/o; ai pio1_7/adc0_10 ? general-purpose digital input/output pin. adc input channel 10 if the digimode bit is set to 0 in the iocon register for this pin. r ? reserved. i/o fc7_rxd_sda_mosi_data ? flexcomm interface 7: usart rxd, i2c sda, spi mosi, i2s data. o ctimer1_mat2 ? 32-bit ctimer1 match output 2. r ? reserved. i ctimer1_cap2 ? 32-bit ctimer1 capture input 2. pio1_8/ adc0_11 c5 28 [4] pu i/o; ai pio1_8/adc0_11 ? general-purpose digital input/out put pin. adc input channel 11 if the digimode bit is set to 0 in the iocon register for this pin. r ? reserved. i/o fc7_txd_scl_miso_ws ? flexcomm interface 7: usart txd, i2c scl, spi miso, i2s ws. o ctimer1_mat3 ? 32-bit ctimer1 match output 3. r ? reserved. i ctimer1_cap3 ? 32-bit ctimer1 capture input 3. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 18 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller pio1_9 - 29 [2] pu i/o pio1_9 ? general-purpose digital input/output pin. r ? reserved. i/o fc3_rxd_sda_mosi ? flexcomm interface 3: usart rxd, i2c sda, spi mosi. i ctimer0_cap2 ? 32-bit ctimer0 capture input 2. r ? reserved. r ? reserved. o usb_up_led ? usb port 2 goodlink led indicator. it is low when the device is configured (non-control endpoints enabled). it is high when the device is not configured or during global suspend. pio1_10 - 30 [2] pu i/o pio1_10 ? general-purpose digital input/output pin. r ? reserved. i/o fc6_txd_scl_miso_ws ? flexcomm interface 6: usart txd, i2c scl, spi miso, i2s ws. o sct0_out4 ? sct0 output 4. pwm output 4. i/o fc1_sck ? flexcomm interface 1: usart or spi clock. r ? reserved. r ? reserved. i usb_frame ? usb start-of-frame signal derived from host signaling. pio1_11 - 42 [2] pu i/o pio1_11 ? general-purpose digi tal input/output pin. r ? reserved. i/o fc6_rts_scl_ssel1 ? flexcomm interface 6: u sart rts, i2c scl, spi ssel1. i ctimer1_cap0 ? 32-bit ctimer1 capture input 0. i/o fc4_sck ? flexcomm interface 4: usart or spi clock. r ? reserved. r ? reserved. i usb_vbus ? monitors the presence of usb bus power. this signal must be high for usb reset to occur. pio1_12 - 51 [2] pu i/o pio1_12 ? general-purpose digital input/output pin. r ? reserved. i/o fc5_rxd_sda_mosi ? flexcomm interface 5: usart rxd, i2c sda, spi mosi. o ctimer1_mat0 ? 32-bit ctimer1 match output 0. i/o fc7_sck ? flexcomm interface 7: usart, spi, or i2s clock. i utick_cap2 ? micro-tick timer capture input 2. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 19 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller pio1_13 - 54 [2] pu i/o pio1_13 ? general-purpose digital input/output pin. r ? reserved. i/o fc5_txd_scl_miso ? flexcomm interface 5: usart txd, i2c scl, spi miso. o ctimer1_mat1 ? 32-bit ctimer1 match output 1. i/o fc7_rxd_sda_mosi_data ? flexcomm interface 7: usart rxd, i2c sda, spi mosi, i2s data. pio1_14 - 57 [2] pu i/o pio1_14 ? general-purpose digital input/output pin. r ? reserved. i/o fc2_rxd_sda_mosi ? flexcomm interface 2: usart rxd, i2c sda, spi mosi. o sct0_out7 ? sct0 output 7. pwm output 7. i/o fc7_txd_scl_miso_ws ? flexcomm interface 7: usart txd, i2c scl, spi miso, i2s ws. pio1_15 - 62 [2] pu i/o pio1_15 ? general-purpose digital input/output pin. o pdm0_clk ? clock for pdm interface 0, for digital microphone. o sct0_out5 ? sct0 output 5. pwm output 5. i ctimer1_cap3 ? 32-bit ctimer1 capture input 3. i/o fc7_cts_sda_ssel0 ? flexcomm interface 7: us art cts, i2c sda, spi ssel0. pio1_16 - 7 [2] pu i/o pio1_16 ? general-purpose digital input/output pin. i pdm0_data ? data for pdm interface 0, digital microphone input. o ctimer0_mat0 ? 32-bit ctimer0 match output 0. i ctimer0_cap0 ? 32-bit ctimer0 capture input 0. i/o fc7_rts_scl_ssel1 ? flexcomm interface 7: u sart rts, i2c scl, spi ssel1. pio1_17 - 10 [2] pu i/o pio1_17 ? general-purpose digital input/output pin. r ? reserved. r ? reserved. r ? reserved. i/o mclk ? mclk input or output for i2s and/or digital microphone. i utick_cap3 ? micro-tick timer capture input 3. usb_dp d2 5 [6] f i/o usb0 bidirectional d+ line. usb_dm d1 6 [6] f i/o usb0 bidirectional d- line. resetn g1 64 [5] pu i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. wakes up the part from deep power-down mode. rtcxin a7 33 - - rtc oscillator input. rtcxout b7 35 - - rtc oscillator output. vrefp b4 22 - - adc positive reference voltage. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 20 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] pu = input mode, pull-up enabled ( pull-up resistor pulls up pin to v dd ). z = high impedance; pull-up or pull-down disabled, ai = analog input, i = input, o = output, f = floating. reset state reflects the pin state at reset without boot code operation. for pin st ates in the different power modes, see section 6.2.2 ? pin states in different power modes ? . for termination on unused pins, see section 6.2.1 ? termination of unused pins ? . [2] 5 v tolerant pad with programmable glitch filter (5 v tolerant if v dd present; if v dd not present, do not exceed 3.6 v); provides digital i/o functions with ttl levels and hyster esis; normal drive strength. see figure 31 . pulse width of spikes or glitches suppressed by input filter is from 3 ns to 16 ns (simulated value). [3] true open-drain pin. i2c-bus pins compliant with the i2c-bus specification for i2c standard mode, i2c fast-mode, and i2c fas t-mode plus. the pin requires an external pull-up to provide output functionality. when powe r is switched off, this pin is floating an d does not disturb the i2c lines. open-drain configurat ion applies to all functions on this pin. [4] 5 v tolerant pin providing standard digita l i/o functions with configurable modes, configurable hysteresis, and analog input . when configured as an analog input, the digital section of t he pin is disabled, and the pin is not 5 v tolerant. [5] reset pad.5 v tolerant pad with glitch filter with hysteresis. pulse width of spikes or glitches suppressed by input filter is from 3 ns to 20 ns (simulated value) [6] 5 v tolerant transparent analog pad. vrefn - 21 - - adc negative reference voltage. v dda a4 23 - - analog supply voltage. v dd c4, f4 8, 24, 34, 56 - - single 1.62 v to 3.6 v power supply powers internal digital functions and i/os. v ss d4, e4 9, 25, 55 - - ground. v ssa a3 20 - - analog ground. table 4. pin description ?continued symbol 49-pin 64-pin reset state [1] type description
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 21 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 6.2.1 termination of unused pins ta b l e 5 shows how to terminate pins that are not used in the application. in many cases, unused pins should be connect ed externally or configured correctly by software to minimize the overall power consumption of the part. unused pins with gpio function should be configured as outputs set to low with their internal pull-up disabled. to configure a gpio pin as output and drive it low, select the gpio function in the iocon register, select ou tput in the gpio dir register, and write a 0 to the gpio port register for that pin. di sable the pull-up in the pin?s iocon register. in addition, it is recommended to configure all gpio pins that are not bonded out on smaller packages as outputs driven low with their internal pull-up disabled. [1] i = input, ia = inactive (no pull-up/pull -down enabled), pu = pull-up enabled, f = floating 6.2.2 pin states in different power modes [1] default and programmed pin states are retained in sleep and deep-sleep modes. table 5. termination of unused pins pin default state [1] recommended termination of unused pins reset i; pu the reset pin can be left unconnected if the application does not use it. all pion_m (not open-drain) i; pu can be left unconnected if driven low and configured as gpio output with pull-up disabled by software. pion_m (i2c open-drain) ia can be left unconnected if driven low and conf igured as gpio output by software. usb_dp f if usb interface is not used, pin can be left unconnected except in deep power-down mode where it must be externally pulled low. usb_dm f if usb interface is not used, pin can be left unconnected except in deep power-down mode where it must be externally pulled low. rtcxin - connect to ground. when grounded, the rtc oscillator is disabled. rtcxout - can be left unconnected. vrefp - tie to v dd . vrefn - tie to v ss . v dda - tie to v dd . v ssa - tie to v ss . table 6. pin states in different power modes pin active sleep deep-sleep deep power-down pion_m pins (not i2c) as configured in the iocon [1] . default: internal pull-up enabled. floating. pio0_23 to pio0_26 (open-drain i2c-bus pins) as configured in the iocon [1] . floating. reset reset function enabled. default: input, internal pull-up enabled.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 22 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7. functional description 7.1 architectural overview the arm cortex-m4 includes three ahb-lite buses, one system bus and the i-code and d-code buses. one bus is dedicated for in struction fetch (i-code), and one bus is dedicated for data access (d-code). the use of two core buses allows for simultaneous operations if concurrent operations target different devices. the lpc5411x uses a multi-layer ahb matrix to connect the arm cortex-m4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave ports of the matrix to be accessed simultaneously by different bus masters. 7.2 arm cortex-m4 processor the arm cortex-m4 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumptio n. the arm cortex-m4 offers many new features, including a thumb-2 instruction set, low interrupt latency, hardware multiply and divide, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. a 3-stage pipeline is employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. 7.3 arm cortex-m4 integrated floating point unit (fpu) the fpu fully supports single-precision add , subtract, multiply, divide, multiply and accumulate, and square root operations. it also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions. the fpu provides floating-point computation functionality that is compliant with the ansi/ieee std 754-2008, ieee st andard for binary fl oating-point arithmetic, referred to as the ieee 754 standard. 7.4 arm cortex-m0+ co-processor the arm cortex-m0+ co-processor offers high performance and very low power consumption. this processor uses a 2-sta ge pipeline von neumann architecture and a small but powerful instruction set providing high-end processing hardware. the processor includes a single-cycle multiplier, an nvic with 32 interrupts, and a se parate system tick timer. 7.5 memory protection unit (mpu) the cortex-m4 includes a memory protection unit (mpu) which can be used to improve the reliability of an embedded system by pr otecting critical data within the user application.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 23 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller the mpu allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses th at could potentially break the system. the mpu separates the memory into distinct regions and implements protection by preventing disallowed accesses. the mpu supports up to eight regions each of which can be divided into eight subregions. accesses to memory locations that are not defined in the mpu regions, or not permitted by the region setting, will cause the memo ry management fault exception to take place. 7.6 nested vectored interrupt c ontroller (nvic) for cortex-m4 the nvic is an integral part of the cortex-m 4. the tight coupling to the cpu allows for low interrupt latency and efficient processing of late arriving interrupts. 7.6.1 features ? controls system exceptions and peripheral interrupts. ? 40 vectored interrupt slots. ? eight programmable interrupt priority leve ls, with hardware priority level masking. ? relocatable vector table using vect or table offset register (vtor). ? non-maskable interrupt (nmi). ? software interr upt generation. 7.6.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. 7.7 nested vectored interrupt c ontroller (nvic) for cortex-m0+ the nvic is an integral part of the cortex -m0+. the tight coupling to the cpu allows for low interrupt latency and efficient processing of late arriving interrupts. 7.7.1 features ? controls system exceptions and peripheral interrupts. ? 32 vectored interrupt slots. ? four programmable interrupt priority leve ls, with hardware pr iority level masking. ? relocatable vector table using vtor. ? non-maskable interrupt (nmi). ? software interr upt generation. 7.7.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 24 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.8 system tick timer (systick) the arm cortex-m4 and arm cortex-m0+ co res include a system tick timer (systick) that is intended to generate a dedicated systick except ion. the clock source for the systick can be the system clock or the systick clock. 7.9 on-chip static ram the lpc5411x supports up to192 kb sram with separate bus master access for higher throughput and individual power control for low-power operation. 7.10 on-chip flash the lpc5411x supports up to 256 kb of on-chip flash memory. 7.11 on-chip rom the 32 kb on-chip rom contains the boot loader and the following application programming interfaces (api): ? in-system programming (isp) and in-application programming (iap) support for flash programming. ? rom-based usb drivers (hid, cdc, msc, and dfu). flash updates via usb is supported. ? supports booting from valid user code in flash, usart, spi, and i 2 c. ? legacy, single, and dual image boot.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 25 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.12 memory mapping the lpc5411x incorporates several distinct memory regions. the apb peripheral area is 64 kb in size and is divided to allow for up to 32 peripherals. each peripheral is allocated 4 kb of space simplifying the address decoding. figure 6 shows the overall map of the entire address space from the user program viewpoint following reset.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 26 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] the private peripheral bus includes cpu peripherals such as the nvic, systick, and the core control registers. [2] the total size of flash and sram is part dependent. see table 1 on page 5. fig 6. lpc5411x memory mapping 0x400a 1000 0x400a 0000 0x4009 d000 0x4009 c000 0x4009 9000 0x4009 8000 0x4009 7000 0x4009 6000 0x4009 5000 0x4009 1000 0x4009 0000 0x4008 c000 0x4008 b000 0x4008 a000 0x4008 9000 0x4008 8000 0x4008 7000 0x4008 6000 0x4008 5000 0x4008 4000 0x4008 3000 0x4008 2000 0x4008 1000 adc (reserved) isp-ap interface (reserved) flexcomm interface 7 flexcomm interface 6 flexcomm interface 5 crc engine (reserved) dmic interface high speed gpio mailbox flexcomm interface 4 flexcomm interface 3 flexcomm interface 2 flexcomm interface 1 apb peripherals active interrupt vectors (reserved) private peripheral bus (1) ahb peripherals asynchronous apb peripherals (reserved) (reserved) (reserved) boot rom (reserved) peripheral bit-band addressing memory space 0xffff ffff 0xe010 0000 0xe000 0000 0x4400 0000 0x4200 0000 0x400a 1000 0x4008 0000 see apb memory map figure 0x4006 0000 0x0004 0000 0x0000 0000 flexcomm interface 0 sctimer / pwm fs usb device (reserved) dma controller (reserved) sram bit-band addressing (reserved) (reserved) sram2 (32 kb) (2) sram1 (64 kb) (2) sram0 (64 kb) (2) sramx (32 kb) (2) apb peripherals on apb bridge 1 apb peripherals on apb bridge 0 0x0400 8000 0x0400 0000 0x0300 8000 0x0300 0000 0x2002 8000 0x2200 0000 0x2001 0000 0x2002 0000 0x2000 0000 0x4002 0000 0x4004 0000 0x2400 0000 0x4000 0000 0x0000 0000 0x0000 00c0 (reserved) (reserved) aaa-022100 256 kb on-chip flash (2) 128 kb on-chip flash (2) 0x0002 0000
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 27 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.13 system control 7.13.1 clock sources the lpc5411x supports two external and three internal clock sources: ? the free running oscillator (fro). ? watchdog oscillator (wdtosc). ? external clock source from the digital i/o pin clkin. ? external rtc 32.768 khz clock. ? output of the system pll. 7.13.1.1 fro the internal fro can be used as a cpu clo ck or a clock source to the system pll. on power-up, or any chip reset, the lpc5411x uses an inte rnal 12 mhz fro as the clock source. software may later swit ch to one of the available clock sources. a selectable 48 mhz or 96 mhz fro is also available as a clock source. the 48 mhz fro can be used as a clock source to the usb. the fro is trimmed to ? 1 % accuracy over the entire voltage and temperature range. 7.13.1.2 watchdog oscillator (wdtosc) the watchdog oscillator is a lo w-power internal oscillator. the wdtosc can be used to provide a clock to the wwdt and to the entire chip. th e watchdog oscillator has a selectable frequency in the range of 6 khz to 1.5 mhz. fig 7. lpc5411x apb memory map 31-21 20 19-13 12 11-9 8 7-0 0x4003 ffff 0x4003 5000 0x4003 4000 0x4002 d000 0x4002 c000 0x4002 9000 0x4002 8000 0x4002 0000 (reserved) (reserved) (reserved) (reserved) rtc flash controller ctimer 2 apb bridge 1 31-15 14 13 12 11-10 9 8 0x4001 ffff 0x4000 f000 0x4000 e000 0x4000 d000 0x4000 c000 0x4000 a000 0x4000 9000 0x4000 8000 0x4000 6000 0x4000 5000 0x4000 4000 0x4000 3000 0x4000 2000 0x4000 1000 0x4000 0000 (reserved) multi-rate timer (reserved) ctimer 0 watchdog timer micro-tick timer ctimer 1 apb bridge 0 7-6 5 4 3 2 1 input muxes gint 1 iocon pin interrupts (pint) (reserved) gint 0 2 syscon 31-10 9 8 7-1 0 0x4005 ffff 0x4004 a000 0x4004 9000 0x4004 8000 0x4004 1000 0x4004 0000 (reserved) ctimer 3 asynch. syscon (reserved) ctimer 4 asynchronous apb bridge aaa-016687
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 28 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.13.1.3 clock input an external square-wave clock source (up to 25 mhz) can be supplied on the digital i/o pin clkin. 7.13.1.4 rtc oscillator an external rtc (32.768 khz) can be used to create the main clock when the pll input or output is selected as the cl ock source to the main clock. 7.13.1.5 system pll the system pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency external clock. the system pll can run from the internal fro 12 mhz output, the external clock input clkin, or the rtc oscillator. the system pll accepts an input clock frequency in the range of 32 khz to 25 mhz. the input frequency is multiplied up to a high frequency with a current controlled oscillator (cco) the pll can be enabled or disabled by software. 7.13.2 clock generation the system control block facilitates the cloc k generation. many clo cking variations are possible. figure 8 gives an overview of th e potential clock options.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 29 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller fig 8. lpc5411x clock generation 000 001 010 pll_clk main_clk main_clk fro_hf 111 none adc clock divider to adc adcclkdiv cpu clock divider system clock to cpu, ahb bus, sync apb, etc. ahbclkdiv adc clock select adcclksel[2:0] system pll (pll0) system pll settings to async apb bridge 000 001 010 pll_clk fro_hf main_clk 111 none usb clock divider to fs usb usbclkdiv usb clock select usbclksel[2:0] 00 01 10 clk_in fro_12m (1) (1) wdt_clk 11 fro_hf 00 10 11 pll_clk 32k_clk main clock select a mainclksela[1:0] 00 01 fro_12m main_clk (1) (1): synchronized multiplexer, see register descriptions for details. apb clock select b asyncapbclkselb[1:0] main clock select b mainclkselb[1:0] 000 001 010 clk_in fro_12m wdt_clk 011 32k_clk 111 none pll clock select syspllclksel[2:0] frg clock divider frgctrl[15:0] 000 001 010 pll_clk main_clk fro_12m 011 fro_hf 111 none frg clock select frgclksel[2:0] 000 001 010 fro_hf fro_12 pll_clk 011 mclk_in 100 frg_clk 111 none aaa-022102 function clock select fxcomclksel[n][2:0] fcn_fclk (function clock of flexcomm [n] clkout divider clkout clkoutdiv 000 001 010 clk_in main_clk wdt_clk 011 fro_hf 100 pll_clk 101 fro_12m 110 32k_clk 111 none clkout select clkoutsela[2:0] 000 001 010 pll_clk fro_hf main_clk 111 none mclk divider mclk pin (output) mclkdiv mclk clock select mclkclksel[2:0] 000 001 010 fro_hf fro_12 pll_clk 011 mclk_in 100 main_clk 101 wdt_clk 32k_clk dmic clock divider to dmic subsystem to clk32k of all flexcomm interfaces (1 per device) dmicclkdiv dmic clock select dmicclksel[2:0] (1 per flexcomm interface) 111 none (up to 8 flexcomm interfaces on these devices)
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 30 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ta b l e 9 describes signals on the clocking diagram. 7.13.3 brownout detection the lpc5411x includes a monitor for the voltage level on the v dd pin. if this voltage falls below a fixed level, the bod sets a flag that can be polled or cause an interrupt. in addition, a separate threshold levels can be selected to cause chip reset and interrupt. 7.13.4 safety the lpc5411x includes a windowed watchdog timer (wwdt), which can be enabled by software after reset. once enabled, the wwdt remains locked and cannot be modified in any way until a reset occurs. 7.14 code security (code read protection - crp) this feature of the lpc5411x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. when needed, crp is invoked by programming a specific pattern into a ded icated flash location. iap commands are not affected by the crp. in addition, isp entry can be invoked by pulling a pin on th e lpc5411x low on reset. this pin is called the isp entry pin. there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors cannot be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. crp3 fully disables any access to the chip via swd and isp. it is up to the user?s application to provide (if needed) flash upda te mechanism using i ap calls or a call to reinvoke isp command to enable a flash update via usart. table 7. clocking diagram signal name descriptions name description 32k_clk the 32 khz output of the rtc oscillator. the 32 kh z clock must be enabled in the rtcoscctrl register. clk_in this is the internal clo ck that comes from the main clk_in pin function. that function must be connected to the pin by selecting it in the iocon block. frg_clk the output of the fractional rate generator. fro_12m the 12 mhz output of the currently selected on-chip fro oscillator. fro_hf the currently selected fro high speed out put. this may be either 96 mhz or 48 mhz. main_clk the main clock used by the cpu an d ahb bus, and potentially many others. mclk_in the mclk input function, when it is connec ted to a pin by selecting it in the iocon block. pll_clk the output of the pll. wdt_clk the output of the watchdog oscillator, which has a se lectable target frequency. it must also be enabled in the pdrincfg0 register. ?none? a tied-off source that should be selected to save power when the output of the rela ted multiplexer is not used.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 31 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 4. in addition to the three crp levels, sampli ng of the isp entry pin for valid user code can be disabled (no_isp mode). for details, see the lpc5411x user manual. 7.15 power control the lpc5411x support a variety of power control features. in active mode, when the chip is running, power and clo cks to selected peripherals can be adjusted for power consumption. in addition, there are four special modes of processor power reduction with different peripherals running: sleep mode, deep-sleep mode, and deep power-down mode, activated by the power mode configure api. 7.15.1 sleep mode in sleep mode, the system clock to the cpu is stopped and execution of instructions is suspended until either a reset or an interrupt occurs. peripheral functions, if selected to be clocked can continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, internal buses, and unused peripherals. the processor state and registers, peripheral registers, and internal sram values are maintained, and the logic levels of the pins remain static. 7.15.2 deep-sleep mode in deep-sleep mode, the system clock to the pr ocessor is disabled as in sleep mode. all analog blocks are powered down by default but can be selected to keep running through the power api if needed as wake-up sources. the main clock and all peripheral clocks are disabled. the fro is disabled. the flash memory is put in standby mode. deep-sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. the processor state and registers, peripheral registers, and internal sram values are maintained, and the logic levels of the pins remain static. gpio pin interrupts, gp io group interrupts, and selected peripherals such as usb, dmic, spi, i2c, usart, wwdt, rtc, micro-tick timer, and bod can be left running in deep sleep mode the fro, rtc oscillator, and t he watchdog oscillator can be left running. in some cases, dma can operate in deep-sleep mode. for more details, see lpc5411x user manual. 7.15.3 deep power-down mode in deep power-down mode, power is shut off to the entire chip except for the rtc power domain and the reset pin. the lpc5411x can wake up from deep power-down mode via the reset pin and the rtc alarm. the alarm1hz flag in rtc control register caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 32 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller generates an rtc wake-up interrupt request, which can wake up the part. during deep power-down mode, the contents of the sram and registers are not retained. all functional pins are tri-stated in deep power-down mode. ta b l e 8 shows the peripheral configuration in reduced power modes. ta b l e 9 shows the wake-up sources for reduced power modes. table 8. peripheral configuration in reduced power modes peripheral reduced power mode sleep deep-sleep deep power-down fro software configured software configured off flash software configured standby off bod software configured software configured off pll software configured off off watchdog osc and wwdt software configured software configured off micro-tick timer software configured software configured off dma active configurable some for operations, see section 7.13.2 off usart software configured off; but can cr eate a wake-up interrupt in synchronous slave mode or 32 khz clock mode off spi software configured off; but can create a wake-up interrupt in slave mode off i2c software configured off; but can create a wake-up interrupt in slave mode off usb software configured software configured off dmic software configured software configured off other digital peripherals software configured off off rtc oscillator software configured software configured software configured table 9. wake-up sources for reduced power modes power mode wake-up source conditions sleep any interrupt enable interrupt in nvic. hwwake certain flexcomm interfac e and dmic subsystem activity.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 33 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller deep-sleep pin interrupts enable pin interrupts in nvic and starter0 and/or starter1 registers. bod interrupt ? enable interrupt in nvic and starter0 registers. ? enable interrupt in bodctrl register. ? configure the bod to keep running in this mode with the power api. bod reset enable reset in bodctrl register. watchdog interrupt ? enable the watchdog oscillator in the pdruncfg0 register. ? enable the watchdog interrupt in nvic and starter0 registers. ? enable the watchdog in the ww dt mod register and feed. ? enable interrupt in wwdt mod register. ? configure the wdtosc to keep running in this mode with the power api. watchdog reset ? enable the watchdog oscillator in the pdruncfg0 register. ? enable the watchdog and watchdog reset in the wwdt mod register and feed. reset pin always available. rtc 1 hz alarm timer ? enable the rtc 1 hz oscillator in the rtcoscctrl register. ? enable the rtc bus clock in the ahbclkctrl0 register. ? start rtc alarm timer by writing a time-out value to the rtc count register. ? enable the rtcalarm interrupt in the starter0 register. rtc 1 khz timer time-out and alarm ? enable the rtc 1 hz oscillator and the rtc 1 khz oscillator in the rtc ctrl register. ? start rtc 1 khz timer by writing a va lue to the wake register of the rtc. ? enable the rtc wake-up interrupt in the starter0 register. micro-tick timer (intended for ultra-low power wake-up from deep-sleep mode ? enable the watchdog oscillator in the pdruncfg0 register. ? enable the micro-tick timer clock by writing to the ahbclkctrl1 register. ? start the micro-tick timer by writing utick ct rl register. ? enable the micro-tick timer interrupt in the starter0 register. i 2 c interrupt interrupt from i 2 c in slave mode. spi interrupt interrupt from spi in slave mode. usart interrupt interrupt from usart in slave or 32 khz mode. usb need clock interrupt interrupt from usb when activity is detected that requires a clock. dma interrupt see the lpc5411x user manual for details of dma-related interrupts. hwwake certain flexcomm interfac e and dmic subsystem activity. deep power-down rtc 1 hz alarm timer ? enable the rtc 1 hz oscillator in the rtc ctrl register. ? start rtc alarm timer by writing a time-out value to the rtc count register. rtc 1 khz timer time-out and alarm ? enable the rtc 1 hz oscillator and the rtc 1 khz oscillator in the rtcoscctrl register. ? enable the rtc bus clock in the ahbclkctrl0 register. ? start rtc 1 khz timer by writing a va lue to the wake register of the rtc. reset pin always available. table 9. wake-up sources for reduced power modes power mode wake-up source conditions
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 34 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.16 general purpose i/o (gpio) the lpc5411x provides two gpio ports with a total of 48 gpio pins. device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically conf igured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the current level of a port pin can be read back no matter what peripheral is selected for that pin. see ta b l e 4 for the default state on reset. 7.16.1 features ? accelerated gpio functions: ? gpio registers are located on the ahb so that the fastest possible i/o timing can be achieved. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction. ? bit-level set, clear, and toggle registers allow a single instruction set, clear or toggle of any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. ? all gpio pins can be selected to create an edge or level-sensitive gpio interrupt request. ? one gpio group interrupt can be triggered by a combination of any pin or pins. 7.17 pin interrupt/pattern engine the pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the nvic. the pattern match engine can be used in conjunction with software to create complex state machines based on pin inputs. any digital pin, independent of the function se lected through the switch matrix can be configured through the syscon bl ock as an input to the pin interrupt or pattern match engine. the registers that control the pin inte rrupt or pattern match engine are located on the i/o+ bus for fast single-cycle access.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 35 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.17.1 features ? pin interrupts: ? up to eight pins can be selected from all gpio pins on ports 0 and 1 as edge-sensitive or level-sensitive interrupt requests. each request creates a separate interrupt in the nvic. ? edge-sensitive interrupt pins can interrup t on rising or falling edges or both. ? level-sensitive interrupt pins can be high-active or low-active. ? level-sensitive interrupt pins can be high-active or low-active. ? pin interrupts can wake up the device from sleep mode and deep-sleep mode. ? pattern match engine: ? up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute to a boolean expression. the boolean expression consists of specified levels and/or transitions on various combinations of these pins. ? each bit slice minterm (product term) comprising of the specified boolean expression can generate its own, dedicated interrupt request. ? any occurrence of a pattern match can al so be programmed to generate an rxev notification to the cpu. the rxev signal can be co nnected to a pin. ? pattern match can be used in conjunctio n with software to create complex state machines based on pin inputs. ? pattern match engine facilities wake-up only fr om active and sleep modes. 7.18 ahb peripherals 7.18.1 dma controller the dma controller allows peripheral-to memory, memory-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional dma transfers for a single source and destination. 7.18.1.1 features ? 20 channels, 19 of which are connected to peripheral dma requests. these come from the flexcomm interface s (usart, spi, i 2 c, and i2s) and digital microphone interfaces. ? dma operations can be triggered by on-chip or off-chip events. ? priority is user selectable for each channel (up to eight priority levels). ? continuous priority arbitration. ? address cache with four entries. ? efficient use of data bus. ? supports single transfers up to 1,024 words. ? address increment options allow packing and/or unpacking data.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 36 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.19 digital serial peripherals 7.19.1 usb 2.0 device controller 7.19.1.1 features ? usb2.0 full-speed device controller. ? supports ten physical (five logical) en dpoints including one control endpoint. ? supports single and double-buffering. ? supports crystal-less operation and ca libration of fro using usb frames. ? each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. ? link power management (lpm) supported. 7.19.2 dmic subsystem 7.19.2.1 features ? pulse-density modulation (pdm) data input for left and/or right channels on 1 or 2 buses. ? flexible decimation. ? 16 entry fifo for each channel. ? dc blocking or unaltered dc bias can be selected. ? data can be transferred using dma from deep-sleep mode without waking up the cpu, then automatically retu rning to deep-sleep mode. ? data can be streamed directly to i 2 s on flexcomm interface 7.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 37 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.19.3 flexcomm interface serial communication each flexcomm interface provides a choice of peripheral functions, one of which the user must choose before the functi on can be configured and used. 7.19.3.1 features ? usart with asynchronous operation or syn chronous master or slave operation. ? spi master or slave, with up to four slave selects. ? i 2 c, including separate master, slave, and monitor functions. ? flexcomm interfaces 6 and 7 support i 2 s function. ? data for usart, spi, and i 2 s traffic uses the flexco mm interface fifo. the i 2 c function does not use the fifo. 7.19.4 usart 7.19.4.1 features ? synchronous mode with master or slave operation. includes data phase selection and continuous clock option. ? maximum bit rates of 6.25 mbit/s in asynchronous mode. ? maximum data rates of 20 mbit/s in synchronous master mode and 16 mbit/s in synchronous slave mode. ? multiprocessor/multidrop (9-bit) mode with software address compare. ? rs-485 transceiver output enable. ? autobaud mode for automatic baud rate detection. ? parity generation and checking: odd, even, or none. ? software selectable oversampling from 5 to 16 clocks in asynchronous mode. ? one transmit and one receive data buffer. ? rts/cts for hardware signaling for automatic flow control. software flow control can be performed using delta cts detect, transmit disable control, and any gpio as an rts output. ? received data and status can optionally be read from a single register. ? break generation and detection. ? receive data is 2 of 3 sample "voting". status flag set when one sample differs. ? built-in baud rate generator with auto-baud function. ? a fractional rate divider is shared among all usarts. ? interrupts available for fifo receive level reached, fi fo transmit level reached, transmit idle, change in receiver break detect, framing error, parity error, overrun, underrun, delta cts detect, and receiver sample noise detected. ? loopback mode for testing of data and flow control. ? in synchronous slave mode, wakes up the part from deep-sleep mode. ? special operating mode allows operation at up to 9600 baud using the 32.768 khz rtc oscillator as the uart clock. this mo de can be used while the device is in deep-sleep mode and can wake-up the device when a character is received. ? usart transmit and receive function s work with the syst em dma controller.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 38 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ? activity on the usart synchronous slave mode allows wake-up from deep-sleep mode on any enabled interrupt 7.19.5 spi serial i/o controller 7.19.5.1 features ? master and slave operation. ? maximum data rate of 48 mbit/s in master mode and 15 mbit/s in slave mode for spi functions. ? data frames of 1 to 16 bits supported direct ly. larger frames supported by software or dma set-up. ? master and slave operation. ? data can be transmitted to a slave without the need to read incoming data. this can be useful while setting up an spi memory. ? control information can optionally be writ ten along with data. this allows very versatile operation, including ?any length? frames. ? four slave select input/outputs with selectable polarity and flexible usage. ? activity on the spi in slave mode allows wake-up from deep-sleep mode on any enabled interrupt. remark: texas instruments ssi and national microwire modes are not supported. 7.19.6 i 2 c-bus interface the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (f or example, an lcd driver) or a transmitter with the capability to both re ceive and send information (suc h as memory). transmitters and/or receivers can operate in either mast er or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.19.7 features ? independent master, slave, and monitor functions. ? bus speeds supported: ? standard mode, up to 100 kbits/s. ? fast-mode, up to 400 kbits/s. ? fast-mode plus, up to 1 mbits/s (on specific i 2 c pins). ? high speed mode, 3.4 mbits/s as a slave only (on specific i 2 c pins). ? supports both multi-master and multi-master with slave functions. ? multiple i2c slave addresses supported in hardware. ? one slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple i 2 c bus addresses. ? 10-bit addressing supported with software assist. ? supports system management bus (smbus). ? separate dma requests for master, slave, and monitor functions.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 39 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ? no chip clocks are required in order to receive and compare an address as a slave, so this event can wake up the device from deep-sleep mode. 7.19.8 i 2 s-bus interface the i 2 s bus provides a standard communication interface for streaming data transfer applications such as digital audio or data collection. the i 2 s bus specification defines a 3-wire serial bus, having one data, one clock, and one word select/frame trigger signal, providing single or dual (mono or stereo) audio data transfer as well as other configurations. in the lpc5411x, the i 2 s function is included in flexcomm interface 6 and flexcomm interface 7. each of these fl excomm interfaces implement four i 2 s channel pairs. the i 2 s interface within one flexcomm interface provides at least one channel pair that can be configured as a master or a slave. other channel pairs, if present, always operate as slaves. all of the channel pairs within one flexcomm interface share one set of i 2 s signals, and are configured together for eit her transmit or receive operation, using the same mode, same data configuration and fram e configuration. all such channel pairs can participate in a time division multiplexing (tdm) arrangement. for cases requiring an mclk input and/or output, this is handled outside of the i 2 s block in the system level clocking scheme. 7.19.8.1 features ? a flexcomm interface may implement one or more i 2 s channel pairs, the first of which could be a master or a slave, and the rest of which would be slaves. all channel pairs are configured together for either transmit or receive and other shared attributes. the number of channel pairs is defined for each flexcomm interface, and may be from 0 to 4. ? configurable data size for all channels within one flexcomm interface, from 4 bits to 32 bits. each channel pair can also be configured independently to act as a single channel (mono as opposed to stereo operation). ? all channel pairs within one flexcomm inte rface share a single bit clock (sck) and word select/frame trigger (ws), and data line (sda). ? data for all i 2 s traffic within one flexcomm interf ace uses the flexcomm interface fifo. the fifo depth is 8 entries. ? left justified and right justified data modes. ? dma support using fi fo level triggering. ? tdm (time division multiplexing) with a seve ral stereo slots and/ or mono slots is supported. each channel pair can act as any data slot. multiple channel pairs can participate as different slots on one tdm data line. ? the bit clock and ws can be selectively inverted. ? sampling frequencies supported depends on the specific device configuration and applications constraints (e.g. system clo ck frequency, pll availability, etc.) but generally supports standard audio data rates. see the data rates section in i2s chapter (um10914) to calculate clock and sample rates. remark: the flexcomm interface function clock frequency should not be above 48 mhz.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 40 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.20 standard counter/t imers (ctimer0 to 4) the lpc5411x includes five general-purpose 32-bit timer/counters. the timer/counter is design ed to count cycles of th e system derived clock or an externally-supplied clock. it can optionally generate interrupts , generate timed dma requests, or perform other actions at spec ified timer values, based on four match registers. each timer/counter al so includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.20.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? up to four 32-bit capture channels per time r, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? the timer and prescaler may be configured to be cleared on a designated capture event. this feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs per timer corresponding to match registers with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? up to two match registers can be used to generate timed dma requests. ? pwm mode using up to three match channels for pwm output. 7.20.2 sctimer/pwm subsystem the sctimer/pwm is a flexible timer module capable of creating complex pwm waveforms and performing other advanced timi ng and control operations with minimal or no cpu intervention. the sctimer/pwm can operate as a single 32-bit counter or as two independent, 16-bit counters in uni-directional or bi-directional m ode. it supports a selection of match registers against which the count value can be compared, and capture registers where the current count value can be recorded when so me pre-defined condition is detected. the sctimer/pwm module supports multiple separate events that can be defined by the user based on some combination of parameters including a match on one of the match registers, and/or a transition on one of the sctimer/pwm inputs or outputs, the direction of count, and other factors.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 41 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller every action that the sctimer/ pwm block can perform occurs in direct response to one of these user-defined events without any software overhead. any event can be enabled to: ? start, stop, or halt the counter. ? limit the counter which means to clear the counter in unidirectional mode or change its direction in bi-directional mode. ? set, clear, or toggle any sctimer/pwm output. ? force a capture of the count value into any capture registers. ? generate an interrupt of dma request. 7.20.2.1 features ? the sctimer/pwm supports: ? eight inputs. ? eight outputs. ? ten match/capture registers. ? ten events. ? ten states. ? counter/timer features: ? each sctimer/pwm is configurable as two 16-bit counters or one 32-bit counter. ? counters clocked by system clock or selected input. ? configurable number of match and capture registers. up to five match and capture registers total. ? ten events. ? ten states. ? upon match and/or an input or output transition create the following events: interrupt; stop, limit, halt the timer or ch ange counting direction; toggle outputs; change the state. ? counter value can be loaded into capture register triggered by a match or input/output toggle.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 42 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ? pwm features: ? counters can be used in conjunction with match registers to toggle outputs and create time-proportioned pwm signals. ? up to eight single-edge or four dual-edge pwm outputs with independent duty cycle and common pwm cycle length. ? event creation features: ? the following conditions define an event: a counter match condition, an input (or output) condition such as an rising or fa lling edge or level, a combination of match and/or input/output condition. ? selected events can limit, halt, start, or stop a counter or change its direction. ? events trigger state changes, output togg les, interrupts, and dma transactions. ? match register 0 can be used as an automatic limit. ? in bi-directional mode, events can be enabled based on the count direction. ? match events can be held until another qualifying event occurs. ? state control features: ? a state is defined by events that can happen in the state while the counter is running. ? a state changes into another state as a result of an event. ? each event can be assigned to one or more states. ? state variable allows sequencing across multiple counter cycles. 7.20.3 windowed watchdog timer (wwdt) the purpose of the watchdog timer is to re set or interrupt the microcontroller within a programmable time if it enters an erroneous state. when enabled, a watchdog reset is generated if the user program fails to feed (reload) the watchdog within a predetermined amount of time. 7.20.3.1 features ? internally resets chip if not reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? programmable 24-bit timer with internal fixed pre-scaler. ? selectable time period from 1,024 watchdog clocks (t wdclk 256 4) to over 67 million watchdog clocks (t wdclk 2 24 4) in increments of four watchdog clocks. ? ?safe? watchdog operation. once enabled, requires a hardware reset or a watchdog reset to be disabled. ? incorrect feed sequence causes i mmediate watchdog event if enabled. ? the watchdog reload value can optionally be protected such that it can only be changed after the ?warning interrupt? time is reached. ? flag to indicate watchdog reset.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 43 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ? the watchdog clock (wdclk) source is a selectable frequency in the range of 6 khz to 1.5 mhz. the accuracy of this clock is lim ited to +/- 40% over temperature, voltage, and silicon processing variations. ? the watchdog timer can be configured to run in deep-sleep mode. ? debug mode. 7.20.4 rtc timer the rtc block has two timers: main rtc timer, and high-resolution/wake-up timer. the main rtc timer is a 32-bit timer that uses a 1 hz clock and is intended to run continuously as a real-time clock. when the timer value re aches a match value, an interrupt is raised. the alarm interrupt can also wake up the part from any low power mode, if enabled. the high-resolution or wake-up timer is a 16-bit timer that uses a 1 khz clock and operates as a one-shot down timer. when the ti mer is loaded, it starts counting down to 0 at which point an interrupt is raised. the interrupt can be used to wake-up the part from any low power modes. this timer is intended to be used for timed wake-up from deep-sleep or deep power-down modes. the high-resolution wake-up timer can be disabled to conserve power if not used. the rtc timer uses the 32.768 khz clock input to create a 1 hz or 1 khz clock. 7.20.4.1 features ? the rtc oscillator has the following clock outputs: ? 32.768 khz clock, selectable fo r system clock and clkout pin. ? 1 hz clock for rtc timing. ? 1 khz clock for high-resolution rtc timing. ? 32-bit, 1 hz rtc counter and associated match register for alarm generation. ? separate 16-bit high-resolution/wake-up timer clocked at 1 khz for 1 ms resolution with a more that one minute maximum time-out period. ? rtc alarm and high-resolution/wake-up ti mer time-out each generate independent interrupt requests. either time-out can wake up the part from any of the low power modes, including deep power-down. 7.20.5 multi-rate timer (mrt) the multi-rate timer (mrt) provides a repetiti ve interrupt timer with four channels. each channel can be programmed with an independent time interval, and each channel operates independently fr om the other channels. 7.20.5.1 features ? 24-bit interrupt timer. ? four channels independently counting down from individually set values. ? repeat interrupt, one-shot interrupt, and one-shot bus stall modes.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 44 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 7.20.6 micro-tick timer (utick) the ultra-low power micro-tick timer, running from the watchdog osc illator, can be used to wake up the device from low power modes. 7.20.6.1 features ? ultra simple timer. ? write once to start. ? interrupt or so ftware polling. ? four capture registers that can be triggered by external pin transitions. 7.21 12-bit analog-to-dig ital converter (adc) the adc supports a resolution of 12-bit and fast conversion rates of up to 5.0 msamples/s. sequences of analog-to-digital conversions can be triggered by multiple sources. possible trigger sources are the sctimer/pwm, external pins, and the arm txev interrupt. the adc supports a variable clocking scheme with clocking synchronous to the system clock or independent, asynchronous clocking for high-speed conversions the adc includes a hardware threshold compar e function with zero-crossing detection. the threshold crossing interrupt is connect ed internally to the sctimer/pwm inputs for tight timing control between the adc and the sctimer/pwm. 7.21.1 features ? 12-bit successive approximation analog to digital converter. ? input multiplexing up to 12 pins. ? two configurable conversion sequ ences with independent triggers. ? optional automatic high/low threshold comparison and ?zero crossing? detection. ? measurement range v refn to v refp (not to exceed v dda voltage level). ? 12-bit conversion rate of 5.0 mhz. options for reduced reso lution at higher conversion rates. ? burst conversion mode for single or multiple inputs. ? synchronous or asynchronous operati on. asynchronous operation maximizes flexibility in choosing the ad c clock frequency, synchron ous mode minimizes trigger latency and can eliminate uncertainty and jitter in response to a trigger. ? a temperature sensor is connected as an alternative input for adc channel 0. 7.22 temperature sensor the temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a complement to absolute temperature (v ctat ) voltage. the output voltage varies inversely with device temperature with an absolute accuracy of better than ? 3 ? c over the full temperature range (-40 ? c to +105 ? c). the temperature sensor is only approximately linear with a slight curvature. the output voltage is measured over different ranges of temperatures and fi t with linear-least-square lines.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 45 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller after power-up, the temperature sensor output must be allowed to settle to its stable value before it can be used as an accurate adc input. for an accurate measurement of the temper ature sensor by the adc, the adc must be configured in single-channel burst mode. the last value of a nine-conversion (or more) burst provides an accurate result. 7.23 emulation and debugging debug and trace functions are integrated into the arm cortex-m4 and arm cortex-m0+. serial wire debug and trace functions are supp orted. the arm cortex-m4 is configured to support up to eight breakpoints and four watc h points. the arm cortex-m0+ is configured to support up to four breakpoints and two watch points. in addition, jtag boundary scan mode is provided. the arm sysreq reset is suppor ted and causes the processor to rese t the peripherals, execute the boot code, restart from address 0x0000 0000, and break at the user entry point. the swd pins are multiplexed with other digital i/o pins. on reset, the pins assume the swd functions by default.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 46 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. c) the limiting values are stress ratings only and operating the pa rt at these values is not recommended and proper operation is not guaranteed. the conditions for functi onal operation are specified in table 20 . [2] maximum/minimum voltage above the maximum operating voltage (see table 20 ) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] the peak current is limited to 25 times the corresponding maximum current. [4] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. [5] v dd present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd is powered down. [6] applies to all 5 v tolerant i/o pins except true open-drain pins. [7] including the voltage on outputs in 3-state mode. table 10. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) on pin v dd [2] ? 0.5 +4.6 v v dda analog supply voltage on pin v dda ? 0.5 +4.6 v v ref reference voltage on pin vrefp - ? 0.5 +4.6 v v i input voltage only valid when the v dd > 1.8 v; 5 v tolerant i/o pins [6][7] ? 0.5 +5.0 v v i input voltage on i2c open-drain pins [5] ? 0.5 +5.0 v usb_dm, usb_dp pins ? 0.5 +5.0 v v ia analog input voltage on digital pins configured for an analog function [8][9] ? 0.5 v dd v i dd total supply current per supply pin [3] -60ma i ss total ground current per ground pin [3] -60ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ? c -100ma v i(rtcx) 32.768 khz oscillator input voltage [2] ? 0.5 +4.6 v t stg storage temperature [9] ? 65 +150 ? c t j(max) maximum junction temperature -+150 ? c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [3] 4000 v
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 47 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [8] an adc input voltage above 3.6 v can be applied for a short ti me without leading to immediate, unrecoverable failure. accumu lated exposure to elevated voltages at 4.6 v must be less than 10 6 s total over the lifetime of the device. applying an elevated voltage to the adc inputs for a long time affects the reliabili ty of the device and reduces its lifetime. [9] it is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [10] dependent on package type. 9. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. table 11. thermal resistance symbol parameter conditions max/min unit lqfp64 package r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air 58 ? 15 % ? c/w single-layer (4.5 in ? 3 in); still air 81 ? 15 % ? c/w r th(j-c) thermal resistance from junction to case 18 ? 15 % ? c/w wlcsp49 package r th(j-a) thermal resistance from junction to ambient jedec (4.5 in ? 4 in); still air 41 ? 15 % ? c/w r th(j-c) thermal resistance from junction to case 0.3 ? 15 % ? c/w t j t amb p d r th j a ? ?? ? ?? + =
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 48 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 10. static characteristics 10.1 general operating conditions [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. table 12. general operating conditions t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit f clk clock frequency internal cpu/system clock - - 100 mhz for usb full-speed device operation 12 - 100 mhz v dd supply voltage (core and external rail) 1.62 - 3.6 v for usb operation only 3.0 - 3.6 v v dda analog supply voltage 1.62 - 3.6 v v refp adc positive reference voltage v dda ?? 2 v 2.0 - v dda v v dda < 2 v v dda -v dda v rtc oscillator pins v i(rtcx) 32.768 khz oscillator input voltage on pin rtcxin ? 0.5 - +3.6 v v o(rtcx) 32.768 khz oscillator output voltage on pin rtcxout ? 0.5 - +3.6 v
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 49 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 10.2 coremark data [1] clock source fro. pll disabled. [2] characterized through bench m easurements using typical samples. [3] compiler settings: keil vision v.5.17., optimization level 3, optimized for time on. [4] see the flashcfg register in the lpc5411x user manual for system clock flash access time settings. [5] flash is powered down [6] sram1 and sram2 powered down. sram0 and sramx powered. table 13. coremark score t amb =25 ? c, v dd = 3.3v parameter conditions typ unit arm cortex-m4 in active mode; arm cortex-m0+ in sleep mode coremark score coremark code executed from sramx; cclk = 12 mhz [1] [2] [3] [5] [6] 2.6 (iterations/s) / mhz cclk = 48 mhz [1] [2] [3] [5] [6] 2.6 (iterations/s) / mhz cclk = 96 mhz [1] [2] [3] [5] [6] 2.6 (iterations/s) / mhz coremark score coremark code executed from flash; cclk = 12 mhz; 1 system clock flash access time. [1] [2] [3] [4] [6] 2.6 (iterations/s) / mhz cclk = 48 mhz; 3 system clock flash access time. [1] [2] [3] [4] [6] 2.4 (iterations/s) / mhz cclk = 96 mhz; 6 system clock flash access time. [1] [2] [3] [4] [6] 2.1 (iterations/s) / mhz arm cortex-m0+ in active mode ; arm cortex-m4 in sleep mode coremark score coremark code executed from sramx; cclk = 12 mhz [1] [2] [3] [5] [6] 2.0 (iterations/s) / mhz cclk = 48 mhz [1] [2] [3] [5] [6] 2.0 (iterations/s) / mhz cclk = 96 mhz [1] [2] [3] [5] [6] 2.0 (iterations/s) / mhz coremark score coremark code executed from flash; cclk = 12 mhz; 1 system clock flash access time. [1] [2] [3] [4] [6] 2.0 (iterations/s) / mhz cclk = 48 mhz; 3 system clock flash access time. [1] [2] [3] [4] [6] 1.9 (iterations/s) / mhz cclk = 96 mhz; 6 system clock flash access time. [1] [2] [3] [4] [6] 1.7 (iterations/s) / mhz
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 50 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller conditions: v dd = 3.3 v; t amb = 25 c; active mode; all peripher als disabled; bod disabled; see the flashcfg register in the lpc5411x, um10914 user manual for syst em clock flash access time settings. measured with keil uvision 5.17. optimization level 3, optimized for time on. 12 mhz, 48 mhz, and 96 mhz: fro enabled; pll disabled. 24 mhz, 36 mhz, 60 mhz, 72 mhz, 84 mhz, and 100 mhz: fro enabled; pll enabled. fig 9. typical coremark score ddd )uhtxhqf\0+] &ruhpdunvfruh & r u h p d u n v f r u h &ruhpdunvfruh lwhudwlrqvv0+] l w h u d w l r q v v 0 + ] lwhudwlrqvv0+] 065$0 0 6 5 $ 0 065$0 0)odvk 0 ) o d v k 0)odvk 065$0 0 6 5 $ 0 065$0 0)odvk 0 ) o d v k 0)odvk
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 51 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 10.3 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions: ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpio dir register. ? write 1 to the gpio clr register to drive the outputs low. ? all peripherals disabled. [1] typical ratings are not guaranteed. typical values listed are at room temperature (25 ? c), 3.3v. [2] clock source fro. pll disabled. [3] characterized through bench m easurements using typical samples. [4] compiler settings: keil vision 5.17., optimization level 0, optimized for time off. [5] prefetch disabled in flashcfg register. sram0 powered. sr am1, sram2, and sramx powered down. all peripheral clocks disabled. [6] flash is powered down; sram0 and sramx are powered; sram1 an d sram2 are powered down. all peripheral clocks disabled. [7] characterized using low power regulation mode. table 14. static characteristics: power consumption in active mode t amb = ? 40 ? c to +105 ? c, unless otherwise specified.1.62 v ? v dd ? 3.6 v. symbol parameter conditions min typ [1] max unit arm cortex-m0+ in active mode ; arm cortex-m4 in sleep mode i dd supply current coremark code executed from sramx; flash powered down: cclk = 12 mhz [2][3][4][6][7] -1.1- ma cclk = 48 mhz [2][3][4][6][7] -3.0- ma cclk = 96 mhz [2][3][4][6] -7.1- ma i dd supply current coremark code executed from flash; cclk = 12 mhz; 1 system clock flash access time. [2][3][4][5][7] -1.3- ma cclk = 48 mhz; 3 system clock flash access time. [2][3][4][5][7] -3.6- ma cclk = 96 mhz; 7 system clock flash access time. [2][3][4][5] -8.0- ma arm cortex-m4 in active mode; arm cortex-m0+ in sleep mode i dd supply current coremark code executed from sramx; flash powered down: cclk = 12 mhz [2][3][4][6][7] -1.3- ma cclk = 48 mhz [2][3][4][6][7] -3.9- ma cclk = 96 mhz [2][3][4][6] -9.3- ma i dd supply current coremark code executed from flash; cclk = 12 mhz; 1 system clock flash access time. [2][3][4][5][7] -1.5- ma cclk = 48 mhz; 3 system clock flash access time. [2][3][4][5][7] -4.6- ma cclk = 96 mhz; 7 system clock flash access time. [2][3][4][5] -9.9- ma
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 52 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] typical ratings are not guaranteed. typical values listed are at room temperature (25 ? c), 3.3v. [2] characterized through bench m easurements using typical samples. [3] clock source fro. pll disabled. all sram powered. compiler settings: keil vision 5.17., opt imization level 0, optimized for time off. conditions: vdd = 3.3 v; tamb = 25 c; active mode; all periphe rals disabled; bod disabled; pr efetch disabled in flashcfg register. see the flashcfg register in the lpc5411x, um10914 user manual for system clock flash access time settings. sram0 and sramx powered. sram1 and sram2 powered down. meas ured with keil uvision 5.17. optimization level 0, optimized for time off. 12 mhz, 48 mhz, and 96 mhz: fro enabled; pll disabled. 24 mhz, 36 mhz, 60 mhz, 72 mhz, 84 mhz, and 100 mhz: fro enabled; pll enabled. fig 10. coremark power consumption: typical ? a/mhz for m4 and m0+ cores ddd )uhtxhqf\0+] ?$0+] ? $ 0 + ] ?$0+] 0)/$6+ 0 ) / $ 6 + 0)/$6+ 065$0 0 6 5 $ 0 065$0 0)/$6+ 0 ) / $ 6 + 0)/$6+ 065$0 0 6 5 $ 0 065$0 table 15. static characteristics: power consumption in sleep mode t amb = ? 40 ? c to +105 ? c, unless otherwise specified.1.62 v ? v dd ? 3.6 v. symbol parameter conditions min typ [1] max unit arm cortex-m4 in sleep mode; arm cortex-m0+ in sleep mode i dd supply current cclk = 12 mhz [2] [3] -900- ? a cclk = 48 mhz [2] [3] -1.6- ma cclk = 96 mhz [2] [3] -3.0- ma
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 53 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] typical ratings are not guaranteed. typical values listed are at room temperature (25 ? c). [2] characterized through bench meas urements using typical samples. v dd = 1.62 v. [3] guaranteed by characterization, not tested in production. v dd = 2.0 v. table 16. static characteristics: power consumpt ion in deep-sleep and deep power-down modes t amb = ? 40 ? c to +105 ? c, 1.62 v ? . v dd ? 2.0 v; unless otherwise specified. symbol parameter conditions min typ [1][2] max [3] unit i dd supply current deep-sleep mode. flash is powered down. sram0 (64 kb) powered. t amb =25 ? c-1017 ? a sram0 (64 kb) powered. t amb = 105 ? c167 sram0 (64 kb), sram1 (64 kb) powered. - 13 - ? a sram0 (64 kb), sram1 (64 kb), sram2 (32 kb) powered. -14 - ? a sram0 (64 kb), sram1 (64 kb), sram2 (32 kb), sramx (32 kb) powered. -16 - ? a deep power-down mode; rtc oscillator input grounded (rtc oscillator disabled). t amb =25 ? c - 290 330 na t amb = 105 ? c--6 ? a rtc oscillator running with external crystal. - 390 - na
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 54 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] typical ratings are not guaranteed. typical values listed are at room temperature (25 ? c). [2] characterized through bench meas urements using typical samples. v dd = 3.3 v. [3] tested in production, v dd = 3.6 v. table 17. static characteristics: power consumpt ion in deep-sleep and deep power-down modes t amb = ? 40 ? c to +105 ? c, 2.7 v ? . v dd ? 3.6 v; unless otherwise specified. symbol parameter conditions min typ [1][2] max [3] unit i dd supply current deep-sleep mode. flash is powered down. sram0 (64 kb) powered. t amb =25 ? c - 12 19 ? a sram0 (64 kb) powered. t amb = 105 ? c - 182 sram0 (64 kb), sram1 (64 kb) powered. - 15 - ? a sram0 (64 kb), sram1 (64 kb), sram2 (32 kb) powered. - 16 - ? a sram0 (64 kb), sram1 (64 kb), sram2 (32 kb), sramx(32 kb) powered. - 18 - ? a deep power-down mode; rtc oscillator input grounded (rtc oscillator disabled). t amb =25 ? c - 360 470 na t amb = 105 ? c--10 ? a rtc oscillator running with external crystal. - 450 - na conditions: all srams disabl ed except sramx (32 kb). fig 11. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd ddd 7hpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 9 9 9
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 55 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] the supply current per peripheral is measured as t he difference in supply current between the peripheral block enabled and the peripheral block disabled using pdruncfg0/1 regi sters. all other blocks are disabled and no code accessing the peripheral is executed. [2] the supply currents are shown for system clock frequencies of 12 mhz, 48 mhz, and 96 mhz. [3] typical ratings are not guaranteed. characteriz ed through bench measurements using typical samples. conditions: rtc disabled (rtc oscillator input grounded) fig 12. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd ddd 7hpshudwxuh?& , '' ' ' , '' ?$ ? $ ?$ 9 9 9 9 9 9 9 9 9 9 9 9 table 18. typical peripheral power consumption [1][2][3] v dd = 3.3 v; t amb = 25 c peripheral i dd in ua fro (12 mhz, 48 mhz, 96 mhz) 100.0 wdt osc 2.0 flash 200.0 bod 2.0 table 19. typical ahb/apb peri pheral power consumption [3][4][5] t amb = 25 c, v dd = 3.3 v; peripheral i dd in ua/mhz i dd in ua/mhz i dd in ua/mhz ahb peripheral cpu: 12 mhz, sync apb bus: 12 mhz cpu: 48 mhz, sync apb bus: 48 mhz cpu: 96mhz, sync apb bus: 96 mhz usb 2.09 2.09 2.09 temperature sens or 0.02 0.01 0.01 dmic 0.17 0.17 0.17 gpio0 [1] 0.65 0.65 0.65 gpio1 [1] 0.56 0.56 0.56 dma 0.34 0.43 0.43 crc 0.50 0.54 0.54 mailbox 0.12 0.12 0.12
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 56 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] turn off the peripheral when the configuration is done. [2] for optimal system power consumption, use fix ed low frequency async apb bus when the cpu is at a higher frequency. [3] the supply current per peripheral is measured as t he difference in supply current between the peripheral block enabled and the peripheral block disabled using asyncapbc lkctrl, ahbclkctrl0/1, and pdruncfg0 registers. all other blocks are disabled and no code accessing the peripheral is executed. [4] the supply currents are shown for system clock frequencies of 12 mhz, 48 mhz, and 96 mhz. [5] typical ratings are not guaranteed. characteriz ed through bench measurements using typical samples. adc0 1.65 1.67 1.67 sctimer/pwm 4.01 4.05 4.04 flexcomm interface 0 (usart, spi, i 2 c) 1.1 1.2 1.2 flexcomm interface1 (usart, spi, i 2 c) 1.2 1.2 1.2 flexcomm interface 2 (usart, spi, i 2 c) 1.2 1.2 1.2 flexcomm interface 3 (usart, spi, i 2 c) 1.1 1.1 1.1 flexcomm interface 4 (usart, spi, i 2 c) 1.2 1.2 1.2 flexcomm interface 5 (usart, spi, i 2 c) 1.3 1.3 1.3 flexcomm interface 6 (usart, spi, i 2 c, i 2 s) 1.3 1.3 1.3 flexcomm interface 7 (usart, spi, i 2 c, i 2 s) 1.3 1.3 1.4 sync apb peripheral cpu: 12 mhz, sync apb bus: 12 mhz cpu: 48 mhz, sync apb bus: 48 mhz cpu: 96mhz, sync apb bus: 96 mhz inputmux [1] 0.87 0.93 0.93 iocon [1] 5.04 5.12 5.12 pint 1.26 1.26 1.26 gint 1.20 1.20 1.20 wwdt 0.28 0.32 0.32 rtc 0.65 0.65 0.66 mrt 0.26 0.34 0.34 utick 0.13 0.16 0.16 ctimer0 0.52 0.50 0.50 ctimer1 0.39 0.46 0.47 ctimer2 0.48 0.52 0.52 fractional rate generator 0.46 0.44 0.44 async apb peripheral cpu: 12 mhz, async apb bus: 12 mhz cpu: 48 mhz, sync apb bus: 12 mhz [2] cpu: 96mhz, async apb bus: 12 mhz [2] ctimer3 0.36 0.36 0.36 ctimer4 0.37 0.38 0.38 table 19. typical ahb/apb peri pheral power consumption [3][4][5] t amb = 25 c, v dd = 3.3 v; peripheral i dd in ua/mhz i dd in ua/mhz i dd in ua/mhz
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 57 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 10.4 pin characteristics table 20. static characteri stics: pin characteristics t amb = ? 40 ? c to +105 ? c, unless otherwise specified. 1.62 v ? v dd ? 3.6 v unless otherwise specif ied. values tested in production unless otherwise specified. symbol parameter conditions min typ [1] max unit reset pin v ih high-level input voltage 0.8 ? v dd -5.0v v il low-level input voltage ? 0.5 - 0.3 ? v dd v v hys hysteresis voltage [1][14] 0.05 ? v dd -- v standard i/o pins input characteristics i il low-level input current v i = 0 v; on-chip pull-up resistor disabled. -3.0180na i ih high-level input current v i =v dd ; v dd = 3.6 v; for resetn pin. 3.0 180 na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -3.0180na v i input voltage pin configured to provide a digital function; v dd ? 1.8 v [3] 0-5.0v v dd = 0 v 0 - 3.6 v v ih high-level input voltage 1.62 v ? v dd < 2.7 v 1.5 - 5.0 v 2.7 v ? v dd ? 3.6 v 2.0 - 5.0 v v il low-level input voltage 1.62 v ? v dd <2.7 v ? 0.5 - +0.4 v 2.7 v ? v dd ? 3.6 v ? 0.5 - +0.8 v v hys hysteresis voltage [14] 0.1 ? v dd -- v output characteristics v o output voltage output active 0 - v dd v i oz off-state output current v o =0v; v o = v dd ; on-chip pull-up/pull-down resistors disabled -3180na v oh high-level output voltage i oh = ? 4 ma; 1.62 v ? v dd < 2.7 v v dd ? 0.4 - - v i oh = ? 6 ma; 2.7 v ? v dd ? 3.6 v v dd ? 0.4 v ol low-level output voltage i ol = 4 ma; 1.62 v ? v dd < 2.7 v - - 0.4 v i ol = 6 ma; 2.7 v ? v dd ? 3.6 v - - 0.4 v i oh high-level output current v oh =v dd ? 0.4 v; 1.62 v ? v dd <2.7 v 4.0 - - ma v oh =v dd ? 0.4 v; 2.7 v ? v dd ? 3.6 v 6.0 - - ma i ol low-level output current v ol = 0.4 v; 1.62 v ? v dd < 2.7 v 4.0 - - ma v ol = 0.4 v; 2.7 v ? v dd ? 3.6 v 6.0 - - ma i ohs high-level short-circuit output current 1.62 v ? v dd < 2.7 v [2][4] --35ma drive high; connected to ground; 2.7 v ? v dd ? 3.6 v - - 87 ma
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 58 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller i ols low-level short-circuit output current 1.62 v ? v dd < 2.7 v [2][4] --30ma drive low; connected to v dd 2.7 v ? v dd ? 3.6 v - - 77 ma weak input pull-up/pull-down characteristics i pd pull-down current v i = v dd 25 80 ? a v i = 5 v [2] 80 100 ? a i pu pull-up current v i = 0 v ? 25 ? 80 ? a v dd < v i < 5 v [2][7] 630 ? a open-drain i 2 c pins v ih high-level input voltage 1.62 v ? v dd < 2.7 v 0.7 ? v dd -- v 2.7 v ? v dd ? 3.6 v 0.7 ? v dd -- v v il low-level input voltage 1.62 v ? v dd < 2.7 v 0 - 0.3 ? v dd v 2.7 v ? v dd ? 3.6 v 0 - 0.3 ? v dd v v hys hysteresis voltage 0.1 ? v dd -- v i li input leakage current v i =v dd [5] -2.53.5 ? a v i =5v - 5.5 10 ? a i ol low-level output current v ol = 0.4 v; pin configured for standard mode or fast mode 4.0 - - ma v ol = 0.4v; pin configured for fast-mode plus 20 - - ma usb_dm and usb_dp pins v i input voltage 0 - v dd v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v z out output impedance [11] 33.0 - 44 ? v oh high-level output voltage [12] 2.8 - - v v ol low-level output voltage [13] --0.3v i oh high-level output current v oh =v dd ? 0.3 v [9][10] 38 - 74 ma v oh =v dd ? 0.3 v [10][11] 6.0 9.0 ma i ol low-level output current v ol = 0.3 v [9][10] 38 - 74 ma v ol = 0.3 v [10][11] 6.0 9.0 ma i ols low-level short-circuit output current drive low; pad connected to ground [10] --100ma i ohs high-level short-circuit output current drive high; pad connected to ground [10] --100ma table 20. static characteri stics: pin characteristics ?continued t amb = ? 40 ? c to +105 ? c, unless otherwise specified. 1.62 v ? v dd ? 3.6 v unless otherwise specif ied. values tested in production unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 59 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltage. [2] based on characterization. not tested in production. [3] with respect to ground. [4] allowed as long as the current limit does not exceed the maximum current allowed by the device. [5] to v ss . [6] the values specified are simulated and absol ute values, including package/bondwire capacitance. [7] the weak pull-up resistor is connected to the v dd rail and pulls up the i/o pin to the v dd level. [8] the value specified is a simulated va lue, excluding package/ bondwire capacitance. [9] without 33 ? ? 2 % series external resistor. [10] the parameter values specified are simulated and absolute values. [11] with 33 ? ? 2 % series external resistor. [12] with 15 k ? ? 5 % resistor to v ss . [13] with 1.5 k ? ? 5% resistor to 3.6 v external pull-up. [14] guaranteed by design, not tested in production. pin capacitance c io input/output capacitance i 2 c-bus pins [8] --6.0pf pins with digital functions only [6] --2.0pf pins with digital and analog functions [6] --7.0pf table 20. static characteri stics: pin characteristics ?continued t amb = ? 40 ? c to +105 ? c, unless otherwise specified. 1.62 v ? v dd ? 3.6 v unless otherwise specif ied. values tested in production unless otherwise specified. symbol parameter conditions min typ [1] max unit fig 13. pin input/output current measurement aaa-010819 + - pin pio0_n i oh ipu - + pin pio0_n i ol i pd v dd a a
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 60 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 10.4.1 electrical pin characteristics conditions: v dd = 1.8 v; on pins pio0_23 to pio0_26. conditions: v dd = 3.3 v; on pins pio0_23 to pio0_26. fig 14. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & & ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & & conditions: v dd = 1.8 v; on standard port pins. conditions: v dd = 3.3 v; on standard port pins. fig 15. typical low-level output current i ol versus low-level output voltage v ol ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & & ddd 9 2/ 9 , 2/ 2 / , 2/ p$ p $ p$ & & & & & & & & & & & &
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 61 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller conditions: v dd = 1.8 v; on standard port pins. conditions: v dd = 3.3 v; on standard port pins. fig 16. typical high-level output voltage v oh versus high-level output source current i oh ddd , 2+ p$ 9 2+ 2 + 9 2+ 9 9 9 & & & & & & & & & & & & ddd , 2+ p$ 9 2+ 2 + 9 2+ 9 9 9 & & & & & & & & & & & & conditions: v dd = 1.8 v; on standard port pins. conditions: v dd = 3.3 v; on standard port pins. fig 17. typical pull-up current i pu versus input voltage v i ddd 9 , 9 , sx s x , sx ?$ ? $ ?$ & & & & & & & & & & & & ddd 9 , 9 , sx s x , sx ?$ ? $ ?$ & & & & & & & & & & & &
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 62 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller conditions: v dd = 1.8v; on standard port pins. conditions: v dd = 3.3 v; on standard port pins. fig 18. typical pull-down current i pd versus input voltage v i ddd 9 , 9 , sg s g , sg ?$ ? $ ?$ & & & & & & & & & & & & ddd 9 , 9 , sg s g , sg ?$ ? $ ?$ & & & & & & & & & & & &
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 63 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 11. dynamic characteristics 11.1 flash memory [1] typical ratings are not guaranteed. [2] number of erase/program cycles. [3] programming times are given for writ ing 256 bytes from ram to the flash. 11.2 i/o pins [1] simulated data. table 21. flash characteristics t amb = ? 40 ? c to +105 ? c, unless otherwise specified. 1.62 v ? v dd ? 3.6 v unless otherwise specified. symbol parameter conditions min typ [1] max unit n endu endurance sector erase/program [2] 10000 - - cycles page erase/program; page in a sector 1000 - - cycles t ret retention time powered 10 - - years unpowered 10 - - years t er erase time page, sector, or multiple consecutive sectors -100-ms t prog programming time [3] -1-ms table 22. dynamic characteristic: i/o pins [1] t amb = ? 40 ? c to +85 ? c unless otherwise specified; 1.62 v ? v dd ? 3.6 v unless otherwise specified. symbol parameter conditions min typ max unit standard i/o pins - normal drive strength t r rise time pin configured as output; slew = 1 (fast mode); 2.7 v ? v dd ? 3.6 v [2][3] 1.0 - 2.5 ns 1.62 v ? v dd ? 1.98 v 1.6 - 3.8 ns t f fall time pin configured as output; slew = 1 (fast mode); 2.7 v ? v dd ? 3.6 v [2][3] 0.9 - 2.5 ns 1.62 v ? v dd ? 1.98 v 1.7 - 4.1 ns t r rise time pin configured as output; slew = 0 (standard mode); 2.7 v ? v dd ? 3.6 v [2][3] 1.9 - 4.3 ns 1.62 v ? v dd ? 1.98 v 2.9 - 7.8 ns t f fall time pin configured as output; slew = 0 (standard mode); 2.7 v ? v dd ? 3.6 v [2][3] 1.9 - 4.0 ns 1.62 v ? v dd ? 1.98 v 2.7 - 6.7 ns t r rise time pin configured as input [4] 0.3 - 1.3 ns t f fall time pin configured as input [4] 0.2 - 1.2 ns
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 64 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [2] simulated using 10 cm of 50 ? pcb trace with 5 pf receiver input. rise and fall times measured between 80 % and 20 % of the full output signal level. [3] the slew rate is configured in t he iocon block the slew bit. see the lpc5411x um10914 user manual. [4] c l = 20 pf. rise and fall times measured between 90 % and 10 % of the full input signal level. 11.3 wake-up process [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the wake-up time measured is the time between when a gpio input pin is trigger ed to wake the device up from the low power modes and from when a gpio output pin is set in the interrupt service routine (isr) wake-up handler. [3] fro enabled, all peripherals off. pll disabled. [4] rtc disabled. wake up from deep power-down causes the part to go through entire reset process. the wake-up time measured is the time between when the reset pin is triggered to wake the device up and when a gpio output pin is set in the reset handler. [5] fro disabled. table 23. dynamic characteristic: typica l wake-up times from low power modes v dd = 3.3 v;t amb =25 ? c; using fro as the system clock. symbol parameter conditions min typ [1] max unit t wake wake-up time from sleep mode [2][3] -2.0 - ? s from deep-sleep mode [2][3][5] -19 - ? s from deep power-down mode; rtc disabled; using reset pin. [4][5] -1.2 -ms
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 65 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 11.4 system pll [1] data based on characterization results, not tested in production. [2] pll set-up requires high-speed start-up and transition to normal mode. lock times are only valid when high-speed start-up settings are applied followed by nor mal mode settings. the procedure for setting up the pll is described in the lpc5411x user manual. [3] pll current measured using lowest cco fr equency to obtain the desired output frequency. table 24. pll lock times and current t amb = ? 40 ? c to +105 ? c. v dd = 1.62 v to 3.6 v. symbol parameter conditions min typ max unit pll configuration: input frequency 12 mhz; output frequency 75 mhz t lock(pll) pll lock time pll set-up procedure followed [2] - - 400 ? s i dd(pll) pll current when locked [1][3] - - 550 ? a pll configuration: input frequency 12 mhz; output frequency 100 mhz t lock(pll) pll lock time pll set-up procedure followed [2] - - 400 ? s i dd(pll) pll current when locked [1][3] - - 750 ? a pll configuration: input frequency 32.768 khz; output frequency 75 mhz t lock(pll) pll lock time - [1] - - 6250 ? s i dd(pll) pll current when locked [1][3] - - 450 ? a pll configuration: input frequency 32.768 khz; output frequency 100 mhz t lock(pll) pll lock time - [1] - - 6250 ? s i dd(pll) pll current when locked [1][3] - - 560 ? a
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 66 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] data based on characterization results, not tested in production. [2] excluding under- and overshoot which ma y occur when the pll is not in lock. [3] a phase difference between the inputs of the pfd (c lkref and clkfb) smaller than the pfd lock criterion means lock output is high. [4] actual jitter dependent on amplitude and spectrum of substrate noise. [5] input clock coming from a crys tal oscillator with less than 250 ps peak-to-peak period jitter. 11.5 fro the fro is trimmed to ? 1 % accuracy over the entire voltage and temperature range. [1] tested in production.the values listed are at room temperature (25 ? c). [2] data based on characterization results, not tested in production. 11.6 rtc oscillator see section 13.5 for connecting the rtc oscillator to an external clock source. [1] parameters are valid over operating te mperature range unless otherwise specified. table 25. dynamic characteristics of the pll [1] t amb = ? 40 ? c to +105 ? c. v dd = 1.62 v to 3.6 v. symbol parameter conditions min typ max unit reference clock input f in input frequency - 32.768 khz - 25 mhz - clock output f o output frequency for pll clkout output [2] 1.2 - 150 mhz d o output duty cycle for pll clkout output 46 - 54 % f cco cco frequency - - - 150 mhz lock detector output ? lock(pfd) pfd lock criterion - [3] 124 ns dynamic parameters at f out = f cco = 100 mhz; standard bandwidth settings j rms-interval rms interval jitter f ref = 10 mhz [4] [5] -1530 ps j pp-period peak-to-peak, period jitter f ref = 10 mhz [4] [5] - 40 80 ps table 26. dynamic characteristic: fro t amb = ? 40 ? c to +105 ? c; 1.62 v ? v dd ? 3.6 v symbol parameter min [2] typ [1] max [2] unit f osc(fro) fro clock frequency 11.88 12 12.12 mhz f osc(fro) fro clock frequency 47.52 48 48.48 mhz f osc(fro) fro clock frequency 95.04 96 96.96 mhz table 27. dynamic characte ristic: rtc oscillator t amb = ? 40 ? c to +105 ? c; 1.62 v ? v dd ? 3.6 v [1] symbol parameter min typ max unit f i input frequency - 32.768 - khz
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 67 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 11.7 watchdog oscillator [1] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ? 40 ? c to +105 ? c) is ? 40 %. [3] actual jitter dependent on amplitude and spectrum of substrate noise. [4] guaranteed by design. not tested in production samples. 11.8 i 2 c-bus [1] guaranteed by design. not tested in production. [2] parameters are valid over oper ating temperature range unless otherwise specified. see the i 2 c-bus specification um10204 for details. [3] thd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowl edge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall times are allowed. table 28. dynamic characterist ics: watchdog oscillator t amb = ? 40 ? c to +105 ? c; 1.62 v ?? v dd ? 3.6 v symbol parameter min typ [1] max unit f osc(int) internal watchdog oscillator frequency [2] 6 - 1500 khz d clkout clkout duty cycle 48 - 52 % j pp-cc peak-peak period jitter [3] [4] - 1 20 ns t start start-up time [4] -4 - ? s table 29. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +105 ? c; 1.62 v ? v dd ? 3.6 v [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4][5][6][7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3][4][8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9][10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 68 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection re sistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time. this maxi mum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] tsu;dat is the data set-up time that is measured with respec t to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. 11.9 i 2 s-bus interface fig 19. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat table 30. dynamic characteristics: i 2 s-bus interface pins [1][4] t amb = ? 40 ? c to 105 ? c; v dd = 1.62 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1.0 ns, slew setting = standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ [3] max unit common to master and slave t wh pulse width high on pins i2 sx_tx_sck and i2sx_rx_sck [5] cclk = 1 mhz to 12 mhz (t cyc /2) -1 - (t cyc /2) +1 ns cclk = 48 mhz to 60 mhz (t cyc /2) -1 - (t cyc /2) +1 ns cclk = 96 mhz (t cyc /2) -1 - (t cyc /2) +1 ns t wl pulse width low on pins i2sx_tx_sck and i2sx_rx_sck [5] cclk = 1 mhz to 12 mhz (t cyc /2) -1 - (t cyc /2) +1 ns cclk = 48 mhz to 60 mhz (t cyc /2) -1 - (t cyc /2) +1 ns cclk = 96 mhz (t cyc /2) -1 - (t cyc /2) +1 ns
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 69 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller master; 1.62 v ? vdd ? 2.0 v t v(q) data output valid time on pin i2sx_tx_sda [2] cclk = 1 mhz to 12 mhz 32.7 - 56.6 ns cclk = 48 mhz to 60 mhz 29.9 - 48.9 ns cclk = 96 mhz 29.0 - 47.2 ns on pin i2sx_ws cclk = 1 mhz to 12 mhz 35.1 - 61.1 ns cclk = 48 mhz to 60 mhz 31.9 - 51.8 ns cclk = 96 mhz 31.0 - 49.7 ns t su(d) data input set-up time on pin i2sx_rx_sda [2] cclk = 1 mhz to 12 mhz 0.0 - - ns cclk = 48 mhz to 60 mhz 0.0 - - ns cclk = 96 mhz 0.0 - - ns t h(d) data input hold time on pin i2sx_rx_sda [2] cclk = 1 mhz to 12 mhz 0.0 - - ns cclk = 48 mhz to 60 mhz 0.0 - - ns cclk = 96 mhz 0.0 - - ns slave; 1.62 v ? vdd ? 2.0 v t v(q) data output valid time on pin i2sx_tx_sda [2] cclk = 1 mhz to 12 mhz 25.8 - 47.0 ns cclk = 48 mhz to 60 mhz 23.0 - 38.9 ns cclk = 96 mhz 22.2 - 37.1 ns t su(d) data input set-up time on pin i2sx_rx_sda [2] cclk = 1 mhz to 12 mhz 0.0 - - ns cclk = 48 mhz to 60 mhz 0.0 - - ns cclk = 96 mhz 0.0 - - ns on pin i2sx_rx_ws cclk = 1 mhz to 12 mhz 0.0 - - ns cclk = 48 mhz to 60 mhz 0.0 - - ns cclk = 96 mhz 0.0 - - ns t h(d) data input hold time on pin i2sx_rx_sda [2] cclk = 1 mhz to 12 mhz 1.0 - - ns cclk = 48 mhz to 60 mhz 1.0 - - ns cclk = 96 mhz 1.0 - - ns on pin i2sx_rx_ws cclk = 1 mhz to 12 mhz 2.0 - - ns cclk = 48 mhz to 60 mhz 2.0 - - ns cclk = 96 mhz 2.0 - - ns table 30. dynamic characteristics: i 2 s-bus interface pins [1][4] t amb = ? 40 ? c to 105 ? c; v dd = 1.62 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1.0 ns, slew setting = standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ [3] max unit
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 70 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] based on characterization; not tested in production. master; 2.7 v ? vdd ? 3.6 v t v(q) data output valid time on pin i2sx_tx_sda [2] cclk = 1 mhz to 12 mhz 24.2 - 40.8 ns cclk = 48 mhz to 60 mhz 22.0 - 32.2 ns cclk = 96 mhz 21.3 - 30.3 ns on pin i2sx_ws cclk = 1 mhz to 12 mhz 24.9 - 44.3 ns cclk = 48 mhz to 60 mhz 22.6 - 34.0 ns cclk = 96 mhz 21.8 - 31.7 ns t su(d) data input set-up time on pin i2sx_rx_sda [2] cclk = 1 mhz to 12 mhz 0.0 - - ns cclk = 48 mhz to 60 mhz 0.0 - - ns cclk = 96 mhz 0.0 - - ns t h(d) data input hold time on pin i2sx_rx_sda [2] cclk = 1 mhz to 12 mhz 1.7 - - ns cclk = 48 mhz to 60 mhz 1.4 - - ns cclk = 96 mhz 1.2 - - ns slave; 2.7 v ? vdd ? 3.6 v t v(q) data output valid time on pin i2sx_tx_sda [2] cclk = 1 mhz to 12 mhz 17.4 - 33.8 ns cclk = 48 mhz to 60 mhz 15.2 - 25.1 ns cclk = 96 mhz 14.5 - 23.0 ns t su(d) data input set-up time on pin i2sx_rx_sda [2] cclk = 1 mhz to 12 mhz 0.0 - - ns cclk = 48 mhz to 60 mhz 0.0 - - ns cclk = 96 mhz 0.0 - - ns on pin i2sx_rx_ws cclk = 1 mhz to 12 mhz 0.0 - - ns cclk = 48 mhz to 60 mhz 0.0 - - ns cclk = 96 mhz 0.0 - - ns t h(d) data input hold time on pin i2sx_rx_sda [2] cclk = 1 mhz to 12 mhz 0.0 - - ns cclk = 48 mhz to 60 mhz 0.0 - - ns cclk = 96 mhz 0.0 - - ns on pin i2sx_rx_ws cclk = 1 mhz to 12 mhz 1.0 - - ns cclk = 48 mhz to 60 mhz 1.0 - - ns cclk = 96 mhz 1.0 - - ns table 30. dynamic characteristics: i 2 s-bus interface pins [1][4] t amb = ? 40 ? c to 105 ? c; v dd = 1.62 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1.0 ns, slew setting = standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ [3] max unit
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 71 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [2] clock divider register (div) = 0x0. [3] typical ratings are not guaranteed. [4] the flexcomm interface function clock frequency s hould not be above 48 mhz. see the data rates section in the i 2 s chapter (um10912) to calculate clock and sample rates. [5] based on simulation. not tested in production. fig 20. i 2 s-bus timing (master) fig 21. i 2 s-bus timing (slave) aaa-026799 i2sx_sck i2sx_tx_sda i2sx_ws t cy(clk) t f t r t wh t wl t v(q) t v(q) t su(d) t h(d) i2sx_rx_sda aaa-026800 t cy(clk) t f t r t wh t su(d) t h(d) t su(d) t h(d) t wl i2sx_sck i2sx_rx_sda i2sx_ws i2sx_tx_sda t v(q)
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 72 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 11.10 spi interfaces the actual spi bit rate depends on the de lays introduced by the external trace, the external device, system clo ck (cclk), and capacitive loading. excluding delays introduced by external device and pcb, the maximum supported bit rate for spi master mode is 48 mbit/s, and the maximum supported bit rate for spi slave mode is 15 mbit/s. table 31. spi dynami c characteristics [1] t amb = ? 40 ? c to 105 ? c; v dd = 1.62 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew set to standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ [2] max unit spi master 1.62 v ? v dd ? 2.0 v t ds data set-up time cclk = 1 mhz to 12 mhz 0 - - ns cclk = 48 mhz to 60 mhz 0 - - ns cclk = 96 mhz 0 - - ns t dh data hold time cclk = 1 mhz to 12 mhz 7 - - ns cclk = 48 mhz to 60 mhz 7 - - ns cclk = 96 mhz 7 - - ns t v(q) data output valid time cclk = 1 mhz to 12 mhz 0 - 5 ns cclk = 48 mhz to 60 mhz 0 - 3 ns cclk = 96 mhz 0 - 2 ns spi slave 1.62 v ? v dd ? 2.0 v t ds data set-up time cclk = 1 mhz to 12 mhz 1 - - ns cclk = 48 mhz to 60 mhz 1 - - ns cclk = 96 mhz 1 - - ns t dh data hold time cclk = 1 mhz to 12 mhz 2 - - ns cclk = 48 mhz to 60 mhz 3 - - ns cclk = 96 mhz 3 - - ns t v(q) data output valid time cclk = 1 mhz to 12 mhz 30 - 58 ns cclk = 48 mhz to 60 mhz 23 - 48 ns cclk = 96 mhz 21 - 45 ns spi master 2.7 v ? v dd ? 3.6 v t ds data set-up time cclk = 1 mhz to 12 mhz 3 - - ns cclk = 48 mhz to 60 mhz 4 - - ns cclk = 96 mhz 4 - - ns t dh data hold time cclk = 1 mhz to 12 mhz 11 - - ns cclk = 48 mhz to 60 mhz 11 - - ns cclk = 96 mhz 10 - - ns t v(q) data output valid time cclk = 1 mhz to 12 mhz 0 - 5 ns cclk = 48 mhz to 60 mhz 0 - 3 ns cclk = 96 mhz 0 - 3 ns
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 73 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] based on characterization; not tested in production. [2] typical ratings are not guaranteed. spi slave 2.7 v ? v dd ? 3.6 v t ds data set-up time cclk = 1 mhz to 12 mhz 2 - - ns cclk = 48 mhz to 60 mhz 1 - - ns cclk = 96 mhz 1 - - ns t dh data hold time cclk = 1 mhz to 12 mhz 1 - - ns cclk = 48 mhz to 60 mhz 1 - - ns cclk = 96 mhz 1 - - ns t v(q) data output valid time cclk = 1 mhz to 12 mhz 20 - 44 ns cclk = 48 mhz to 60 mhz 15 - 32 ns cclk = 96 mhz 13 - 30 ns table 31. spi dynami c characteristics [1] t amb = ? 40 ? c to 105 ? c; v dd = 1.62 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew set to standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ [2] max unit fig 22. spi master timing sck (cpol = 0) mosi (cpha = 1) ssel miso (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid mosi (cpha = 0) miso (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014969 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb)
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 74 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller fig 23. spi slave timing sck (cpol = 0) miso (cpha = 1) ssel mosi (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid miso (cpha = 0) mosi (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014970 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb)
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 75 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 11.11 usart interface the actual usart bit rate depends on the de lays introduced by the external trace, the external device, system clo ck (cclk), and capacitive loading. excluding delays introduced by external device and pcb, the maximum supported bit rate for usart master synchronous mode is 20 mbit/s, and the maximum supported bit rate for usart slave synchronous mode is 16 mbit/s table 32. usart dynamic characteristics [1] t amb = ? 40 ? c to 105 ? c; v dd = 1.62 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew set to standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ [2] max unit usart master (in synchronous mode) 1.62 v ? v dd ? 2.0 v t su(d) data input set-up time cclk = 1 mhz to 12 mhz 45 - - ns cclk = 48 mhz to 60 mhz 39 - - ns cclk = 96 mhz 38 - - ns t h(d) data input hold time cclk = 1 mhz to 12 mhz 0 - - ns cclk = 48 mhz to 60 mhz 0 - - ns cclk = 96 mhz 0 - - ns t v(q) data output valid time cclk = 1 mhz to 12 mhz 2 - 9 ns cclk = 48 mhz to 60 mhz 1 - 5 ns cclk = 96 mhz 1 - 4 ns usart slave (in synchronous mode) 1.62 v ? v dd ? 2.0 v t su(d) data input set-up time cclk = 1 mhz to 12 mhz 1 - - ns cclk = 48 mhz to 60 mhz 1 - - ns cclk = 96 mhz 1 - - ns t h(d) data input hold time cclk = 1 mhz to 12 mhz 2 - - ns cclk = 48 mhz to 60 mhz 3 - - ns cclk = 96 mhz 3 - - ns t v(q) data output valid time cclk = 1 mhz to 12 mhz 30 - 55 ns cclk = 48 mhz to 60 mhz 23 - 46 ns cclk = 96 mhz 22 - 46 ns usart master (in synchronous mode) 2.7 v ? v dd ? 3.6 v t su(d) data input set-up time cclk = 1 mhz to 12 mhz 35 - - ns cclk = 48 mhz to 60 mhz 27 - - ns cclk = 96 mhz 25 - - ns t h(d) data input hold time cclk = 1 mhz to 12 mhz 0 - - ns cclk = 48 mhz to 60 mhz 0 - - ns cclk = 96 mhz 0 - - ns t v(q) data output valid time cclk = 1 mhz to 12 mhz 2 - 9 ns cclk = 48 mhz to 60 mhz 2 - 5 ns cclk = 96 mhz 1 - 4 ns
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 76 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] based on characterization; not tested in production. [2] typical ratings are not guaranteed. 11.12 sctimer/pwm output timing usart slave (in synchronous mode) 2.7 v ? v dd ? 3.6 v t su(d) data input set-up time cclk = 1 mhz to 12 mhz 2 - - ns cclk = 48 mhz to 60 mhz 1 - - ns cclk = 96 mhz 1 - - ns t h(d) data input hold time cclk = 1 mhz to 12 mhz 2 - - ns cclk = 48 mhz to 60 mhz 1 - - ns cclk = 96 mhz 1 - - ns t v(q) data output valid time cclk = 1 mhz to 12 mhz 19 - 42 ns cclk = 48 mhz to 60 mhz 14 - 31 ns cclk = 96 mhz 13 - 28 ns table 32. usart dynamic characteristics [1] t amb = ? 40 ? c to 105 ? c; v dd = 1.62 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew set to standard mode for all pins; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ [2] max unit fig 24. usart timing un_sclk (clkpol = 0) txd rxd t cy(clk) t su(d) t h(d) t v(q) start bit0 t vq) un_sclk (clkpol = 1) start bit0 bit1 bit1 aaa-015074 table 33. sctimer/pwm output dynamic characteristics t amb = ? 40 ? c to 105 ? c; 1.62 v ? v dd ? 3.6 v c l = 30 pf. simulated skew (over process, voltage, and temperature) of any two sct fixed-pin output signals; sampled at 10 % and 90 % of the signal level; values guaranteed by design. symbol parameter conditions min typ max unit t sk(o) output skew time - - - 2.7 ns
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 77 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 11.13 dmic subsystem [1] based on simulated values and for 2.7 v to 3.6 v. 11.14 usb interface characteristics table 34. dynamic characteristics t amb = ? 40 ? c to 105 ? c; v dd = 1.62 v to 3.6 v; c l = 30 pf balanced loading on all pins; input slew = 1 ns, slew set to standard mode for all pins; bypass bit = 0; parameters sampled at the 90 % and 10 % level of the rising or falling edge. symbol parameter conditions min typ [1] max unit t ds data set-up time cclk = 1 mhz to 12 mhz - 23 - ns cclk = 48 mhz to 60 mhz - 13 - ns cclk = 96 mhz - 9 - ns t dh data hold time cclk = 1 mhz to 12 mhz - 0 - ns cclk = 48 mhz to 60 mhz - 0 - ns cclk = 96 mhz - 0 - ns fig 25. dmic timing diagram aaa-017025 clock data t su t dh table 35. dynamic characteris tics: usb pins (full-speed) c l = 50 pf; r pu = 1.5 k ? on d+ to v dd , unless otherwise specified; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 4.0 - 20 ns t f fall time 10 % to 90 % 4.0 - 20 ns t frfm differential rise and fall time match- ing t r /t f 90 - 111.11 % v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 26 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 26 ? 2-+5ns t jr1 receiver jitter to next transition ? 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % ? 9-+9ns t eopr1 eop width at receiver must reject as eop; see figure 26 [1] 40 - ns t eopr2 eop width at receiver must accept as eop; see figure 26 [1] 82 --ns
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 78 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] characterized but not implemented as production test. guaranteed by design. fig 26. differential da ta-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 79 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 12. analog characteristics 12.1 bod table 36. bod static characteristics t amb =25 ? c; based on characterization; not tested in production. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 0 assertion - 1.97 - v de-assertion - 2.11 - v v th threshold voltage interrupt level 1 assertion - 2.36 - v de-assertion - 2.51 - v reset level 1 assertion - 1.77 - v de-assertion - 1.92 - v v th threshold voltage interrupt level 2 assertion - 2.66 - v de-assertion - 2.80 - v reset level 2 assertion - 1.92 - v de-assertion - 2.06 - v v th threshold voltage interrupt level 3 assertion - 2.95 - v de-assertion - 3.09 - v reset level 3 assertion - 2.21 - v de-assertion - 2.36 - v
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 80 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 12.2 12-bit adc characteristics [1] based on characterization; not tested in production. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [3] the input resistance of adc channels 6 to 11 is higher than adc channels 0 to 5. [4] c ia represents the external capacitance on t he analog input channel for sampling speeds of 5.0 msamples/s. no parasitic capacitances included. [5] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 27 . [6] the integral non-linearity (e l(adj) ) is the peak difference between the c enter of the steps of the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 27 . [7] the offset error (e o ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. see figure 27 . table 37. 12-bit adc static characteristics t amb = ? 40 ? c to +105 ? c; 1.62 v ? v dd ? 3.6 v; v ssa = vrefn = gnd. adc calibrated at t amb = 25 ?? c. symbol parameter conditions min typ [2] max unit v ia analog input voltage [3] 0- v dda v c ia analog input capacitance [4] -5- pf f clk(adc) adc clock frequency -80 mhz f s sampling frequency - - 5.0 msamples/s e d differential linearity error 1.62 v ? v dda ? 3.6 v 1.62 v ? vrefp ? 3.6 v f clk(adc) = ? 72 mhz [1][5] - ? 3.0 - lsb 2.0 v ? v dda ? 3.6 v 2.0 v ? vrefp ? 3.6 v f clk(adc) = 80 mhz [1][5] - ? 3.0 - lsb v dda = vrefp = 1.62 v f clk(adc) = 80 mhz [1][5] - ? 7.1 - lsb e l(adj) integral non-linearity 1.62 v ? v dda ? 3.6 v 1.62 v ? vrefp ? 3.6 v f clk(adc) ? 72 mhz [1][6] - ? 5.0 - lsb 2.0 v ? v dda ? 3.6 v 2.0 v ? vrefp ? 3.6 v f clk(adc) = 80 mhz [1][6] - ? 4.0 - lsb v dda = vrefp = 1.62 v f clk(adc) = 80 mhz [1][6] - ? 9.0 - lsb e o offset error calibration enabled [1][7] - ? 1.2 - mv v err(fs) full-scale error voltage 1.62 v ? v dda ? 2.0 v 1.62 v ? vrefp ? 2.0 v [1][8] - ? 3.5 lsb 2.0 v ? v dda ? 3.6 v 2.0 v ? vrefp ? 3.6 v - ? 2.0 lsb z i input impedance f s = 5.0 msamples/s [9][10] 17.0 - - k ?
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 81 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [8] the full-scale error voltage or gain error (e g ) is the difference between the st raight-line fitting the actual transfer curve after removing offset error, and the stra ight line which fits the ideal transfer curve. see figure 27 . [9] t amb = 25 ? c; maximum sampling frequency f s = 5.0 msamples/s and analog input capacitance c ia =5pf. [10] input impedance z i is inversely proportional to the sampling frequency and the total input capacity including c ia and c io : z i ? 1 / (f s ? c i ). see table 20 for c io . see figure 28 . (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 27. 12-bit adc characteristics aaa-016908 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp - vrefn 4096 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 82 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller table 38. adc sampling times [1] t amb = -40 ? c to 85 ? c; 1.62 v ? v dda ? 3.6 v; 1.62 v ? v dd ? 3.6 v symbol parameter conditions min typ max unit adc inputs adc_5 to adc_0 (fast channels); adc resolution = 12 bit t s sampling time z o < 0.05 k ? [3] 20 - - ns 0.05 k ? ? z o < 0.1 k ? 23 - - ns 0.1 k ? ? z o < 0.2 k ? 26 - - ns 0.2 k ? ? z o < 0.5 k ? 31 - - ns 0.5 k ? ? z o < 1 k ? 47 - - ns 1 k ? ? z o < 5 k ? 75 - - ns adc inputs adc_5 to adc_0 (fast channels); adc resolution = 10 bit t s sampling time z o < 0.05 k ? [3] 15 - - ns 0.05 k ? ? z o < 0.1 k ? 18 - - ns 0.1 k ? ? z o < 0.2 k ? 20 - - ns 0.2 k ? ? z o < 0.5 k ? 24 - - ns 0.5 k ? ? z o < 1 k ? 38 - - ns 1 k ? ? z o < 5 k ? 62 - - ns adc inputs adc_5 to adc_0 (fast channels); adc resolution = 8 bit t s sampling time z o < 0.05 k ? [3] 12 - - ns 0.05 k ? ? z o < 0.1 k ? 13 - - ns 0.1 k ? ? z o < 0.2 k ? 15 - - ns 0.2 k ? ? z o < 0.5 k ? 19 - - ns 0.5 k ? ? z o < 1 k ? 30 - - ns 1 k ? ? z o < 5 k ? 48 - - ns adc inputs adc_5 to adc_0 (fast channels); adc resolution = 6 bit t s sampling time z o < 0.05 k ? [3] 9- - ns 0.05 k ? ? z o < 0.1 k ? 10 - - ns 0.1 k ? ? z o < 0.2 k ? 11 - - ns 0.2 k ? ? z o < 0.5 k ? 13 - - ns 0.5 k ? ? z o < 1 k ? 22 - - ns 1 k ? ? z o < 5 k ? 36 - - ns adc inputs adc_11 to adc_6 (slow ch annels); adc resolution = 12 bit t s sampling time z o < 0.05 k ? [3] 43 - - ns 0.05 k ? ? z o < 0.1 k ? 46 - - ns 0.1 k ? ? z o < 0.2 k ? 50 - - ns 0.2 k ? ? z o < 0.5 k ? 56 - - ns 0.5 k ? ? z o < 1 k ? 74 - - ns 1 k ? ? z o < 5 k ? 105 - - ns
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 83 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] characterized through simulation. not tested in production. [2] the adc default sampling time is 2.5 adc clock cycles. to match a given analog source output impedance, the sampling time can be extended by addi ng up to seven adc clock cycles for a maximum sampling time of 9.5 adc clock cycles. see the tsamp bits in the adc ctrl register. [3] z o = analog source output impedance. 12.2.1 adc input impedance figure 28 shows the adc input impedance. in this figure: ? adcx represents slow adc input channels 6 to 11. ? adcy represents fast adc input channels 0 to 5. ? r 1 and r sw are the switch-on resistance on the adc input channel. ? if fast channels (adc inputs 0 to 5) are selected, the adc input signal goes through r sw to the sampling capacitor (c ia ). ? if slow channels (adc inputs 6 to 11) are selected, the adc input signal goes through r 1 + r sw to the samplin g capacitor (c ia ). ? typical values, r 1 = 487 ? , r sw = 278 ? ? see ta b l e 2 0 for c io . ? see ta b l e 3 7 for c ia . adc inputs adc_11 to adc_6 (slow ch annels); adc resolution = 10 bit t s sampling time z o < 0.05 k ? [3] 35 - - ns 0.05 k ? ? z o < 0.1 k ? 38 - - ns 0.1 k ? ? z o < 0.2 k ? 40 - - ns 0.2 k ? ? z o < 0.5 k ? 46 - - ns 0.5 k ? ? z o < 1 k ? 61 - - ns 1 k ? ? z o < 5 k ? 86 - - ns adc inputs adc_11 to adc_6 (slow ch annels); adc resolution = 8 bit t s sampling time z o < 0.05 k ? [3] 27 - - ns 0.05 k ? ? z o < 0.1 k ? 29 - - ns 0.1 k ? ? z o < 0.2 k ? 32 - - ns 0.2 k ? ? z o < 0.5 k ? 36 - - ns 0.5 k ? ? z o < 1 k ? 48 - - ns 1 k ? ? z o < 5 k ? 69 - - ns adc inputs adc_11 to adc_6 (slow ch annels); adc resolution = 6 bit t s sampling time z o < 0.05 k ? [3] 20 - - ns 0.05 k ? ? z o < 0.1 k ? 22 - - ns 0.1 k ? ? z o < 0.2 k ? 23 - - ns 0.2 k ? ? z o < 0.5 k ? 26 - - ns 0.5 k ? ? z o < 1 k ? 36 - - ns 1 k ? ? z o < 5 k ? 51 - - ns table 38. adc sampling times ?continued [1] t amb = -40 ? c to 85 ? c; 1.62 v ? v dda ? 3.6 v; 1.62 v ? v dd ? 3.6 v symbol parameter conditions min typ max unit
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 84 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 12.3 temperature sensor [1] absolute temperature accuracy. [2] based on simulation. fig 28. adc input impedance dac adc r sw r 1 c ia adcx adcy c io c io aaa-017600 table 39. temperature sensor stati c and dynamic characteristics v dd = v dda = 1.62 v to 3.6 v symbol parameter conditions min typ max unit dt sen sensor temperature accuracy t amb = ? 40 ? c to +105 ? c [1] -- 3 ? c e l linearity error t amb = ? 40 ? c to +105 ? c- - 3 ? c t s(pu) power-up settling time to 99% of temperature sensor output value [2] -10 15 ? s
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 85 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller [1] measured over typical samples. [2] measured for samples over process corners. table 40. temperature sensor linear-least-square (lls) fit parameters v dd = v dda = 1.62 v to 3.6 v fit parameter range min typ max unit lls slope t amb = ? 40 ? c to +105 ? c [1] --2.0-mv/ ? c lls intercept at 0 ? ct amb = ? 40 ? c to +105 ? c [1] - 590.0 - mv value at 30 ? c [2] 521.0 - 540.0 mv v dd = v dda 3.3 v; measured on matrix samples. fig 29. lls fit of the temperature sensor output voltage ddd 7hpshudwxuh?& 9 r 9 r p9 p 9 p9 //6ilw / / 6 i l w //6ilw
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 86 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 13. application information 13.1 start-up behavior figure 30 shows the start-up timing after reset. the fro 12 mhz oscillator provides the default clock at reset and provides a clean system clock shortly af ter the supply pins reach operating voltage. 13.2 standard i/o pi n configuration figure 31 shows the possible pin modes for standard i/o pins: ? digital output driver: enabled/disabled. ? digital input: pull- up enabled/disabled. ? digital input: pull-down enabled/disabled. fig 30. start-up timing table 41. typical start-up timing parameters parameter description value t a fro start time ? 20 ? s t b internal reset de-asserted 151 ? s t c legacy image 931 ? s single image without crc 904 dual image without crc 952 aaa-023995 valid threshold = 1.62 v processor status v dd fro status internal reset gnd boot time user code boot code execution finishes; user code starts fro starts supply ramp-up time t b s t a s t c s
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 87 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ? digital input: repeater mode enabled/disabled. ? z mode; high impedance (no cross-bar currents for floating inputs). the default configuration for standard i/o pi ns is z mode. the weak mos devices provide a drive capability equivalent to pull-up and pull-down resistors. the glitch filter rejects pulses of typical 12 ns width. fig 31. standard i/o and reset pin configuration aaa-017273 pin configured as digital output open-drain enable output enable data output pin configured as digital input pin configured as analog input digital input analog input enable input invert enable filter glitch filter pin esd esd strong pull-up v dd v dd v dd strong pull-down pull-down enable pull-up enable weak pull-up repeater mode enable enable analog input weak pull-down
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 88 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 13.3 connecting power, clo cks, and debug functions (1) see section 13.5 ? rtc oscillator ? for the values of c3 and c4. (2) position the decoupling capacitors of 0.1 f and 0.01 f as close as possible to the v dd pin. add one set of decoupling capacitors to each v dd pin. (3) position the decoupling capacitors of 0.1 f as close as possible to the vrefn and v dda pins. the 10 f bypass capacitor filters the power line. tie v dda and vrefp to v dd if the adc is not used. tie vrefn to v ss if adc is not used. (4) uses the arm 10-pin interface for swd. (5) when measuring signals of low frequency, use a low-pass filter to remove noise and to improve adc performance. also see ref. 1 . (6) external pull-up resistors on swdio and swclk pins are opt ional because these pins hav e an internal pull-up enabled by default. fig 32. power, clock, and debug connections swdio/pio0_17 swclk/pio0_16 resetn v ss v ssa pio0_31 adcx rtcxin rtcxout v dd (2 to 4 pins) v dda vrefp vrefn lpc5411x 3.3 v 3.3 v dgnd dgnd agnd 1 3 5 7 9 2 4 6 8 10 (4) (5) dgnd dgnd dgnd c3 c4 (1) (2) (3) (3) 0.01 f 0.1 f 3.3 v dgnd 10 f 0.1 f 3.3 v agnd agnd agnd 10 f 0.1 f 0.1 f isp select pins n.c. n.c. n.c. swd connector aaa-022103 pio0_4 pio1_6 3.3 v ~10 k - 100 k 3.3 v ~10 k - 100 k (6) (6)
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 89 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 13.4 i/o power consumption i/o pins can contribute to the overall static and dynamic po wer consumption of the part. if pins are configured as digital inputs with t he pull-up resistor enabled, a static current can flow depending on the voltage level at the pin. this current can be obtained using the parameters i pu and i pd given in ta b l e 2 0 . if pins are configured as digital outputs, the static current is obtained from parameters ioh and iol shown in ta b l e 2 0 , and any external load connected to the pin. when an i/o pin switches in an applicati on, it contributes to the dynamic power consumption because the v dd supply provides the current to charge and discharge all internal and external capacitive loads connected to the pin. the contribution from the i/o switching current i sw can be calculated as follows for any given switching frequency f sw if the external capacitive load (c ext ) is known (see ta b l e 2 0 for the internal i/o capacitance): i sw = v dd x f sw x (c io + c ext )
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 90 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 13.5 rtc oscillator in the rtc oscillator circuit, only the crystal (xtal) and the capacitances c x1 and c x2 need to be connected externally on rtcxin and rtcxout. see figure 33 . for best results, it is very critical to sele ct a matching crystal fo r the on-chip oscillator. load capacitance (cl), series resistance (rs), and drive level (dl) are important parameters to consider while choosing the cr ystal. after selecting the proper crystal, the external load capacitor c x1 and c x2 values can also be gen erally determined by the following expression: c x1 = c x2 = 2c l ? (c pad + c parasitic ) where: c l - crystal load capacitance c pad - pad capacitance of the rtcxin and rtcxout pins (~3 pf). c parasitic ? parasitic or stray capacitance of external circuit. although c parasitic can be ignored in general, the actual board layout and placement of external components influences the optimal values of external load capacitors. therefore, it is recommended to fine tune the values of external load capacitors on actual hardware board to get the accurate clock frequency. for fine tuning, output the rtc clock to one of the gpios and optimize the va lues of external load capacitors for minimum frequency deviation. fig 33. rtc oscillator components aaa-018147 lpc5411x rtcxin rtcxout c x2 c x1 xtal = c l c p r s l
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 91 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 13.5.1 rtc printed circuit board (pcb) design guidelines ? connect the crystal and external load capacitors on the pcb as close as possible to the oscillator input and output pins of the chip. ? the length of traces in the o scillation circuit should be as short as possible and must not cross other signal lines. ? ensure that the load capacitors cx1, cx2, and cx3, in case of third overtone crystal usage, have a common ground plane. ? loops must be made as small as possible to minimize the noise coupled in through the pcb and to keep the parasitics as small as possible. ? lay out the ground (gnd) pattern under crystal unit. ? do not lay out other signal lines under crystal unit for multi-layered pcb. 13.6 suggested usb interface solutions the usb device can be connected to the usb as self-powered device (see figure 34 ) or bus-powered device (see figure 35 ). on the lpc5411x, the usb_vbus pin is 5 v tolerant only when v dd is applied and at operating voltage level. therefore, if the usb_vbus function is connected to the usb connector and the device is self-powered , the usb_vbus pin must be protected for situations when v dd = 0 v. if v dd is always at operating level while vbus = 5 v, the usb_vbus pin can be connected directly to the vbus pin on the usb connector. for systems where v dd can be 0 v and vbus is directly applied to the vbus pin, precautions must be taken to reduce the voltage to below 3.6 v, which is the maximum allowable voltage on the usb_vbus pin in this case. one method is to use a voltage divider to connect the usb_vbus pin to the vbus on the usb connector. the voltage divider ratio s hould be such that the usb_vbus pin is greater than 0.7 v dd to indicate a logic high while below the 3.6 v allowable maximum voltage. for the following operating conditions vbus max = 5.25 v v dd = 3.6 v, the voltage divider should provide a reduction of 3.6 v/5.25 v or ~0.686 v.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 92 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller the internal pull-up (1.5 k ? ) can be enabled by setting the dcon bit in the devcmdstat register to prevent the usb fr om timing out when there is a significant delay between power-up and handling usb traf fic. external circuitry is not required. fig 34. usb interface on a self-powered device where usb_vbus = 5 v lpcxxxx v dd r1 1.5 k aaa-023996 usb-b connector usb_dp usb_dm usb_vbus v ss r s = 33 r s = 33 usb r2 r3 d+ d- two options exist for connecting vbus to the usb_vbus pin: (1) connect the regulator output to usb_vbus. in this case , the usb_vbus signal is high whenever the part is powered. (2) connect the vbus signal directly from t he connector to the usb_vbus pin. in this case, 5 v are applied to the usb_vbus pin while the regulator is ramping up to supply v dd . since the usb_vbus pin is only 5 v tolerant when v dd is at operating level, this connection can degrade the performance of the part over its li fetime. simulation shows that lifetime is reduced to 15 years at t amb = 45 c and 8 years at t amb = 55 c assuming that usb_vbus = 5 v is applied continuously while v dd = 0 v. fig 35. usb interface on a bus-powered device regulator vbus lpcxxxx v dd r1 1.5 k aaa-023997 usb-b connector usb_dp usb_dm v ss usb_vbus (2) usb_vbus (1) usb d- r s = 33 r s = 33 d+
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 93 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 14. package outline fig 36. wlcsp49 package outline references outline version european projection issue date iec jedec jeita - - - sot1444-5_po unit mm max nom min 0.565 0.525 0.485 0.23 0.20 0.17 0.29 0.26 0.23 3.47 3.44 3.41 3.47 3.44 3.41 2.4 2.4 0.05 a dimensions (mm are the original dimensions) a 1 a 2 0.350 0.325 0.300 bde 0.03 y e 0.4 e 1 e 2 v 0.015 w ball a1 index area ball a1 index area x e 2 e detail x c y e 1 e b a c b ? v c ? w d 7 6 5 4 3 2 1 b d e a a a 2 a 1 15-01-30 16-01-20 sot1444-5 wlcsp49: wafer level chip-scale package; 49 bumps; 3.44 x 3.44 x 0.525 mm (backside coating included) scale 0 3 mm sot1444-5 note backside coating 25 m f e g c b a
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 94 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller fig 37. lqfp64 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 95 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 15. soldering fig 38. wlcsp49 soldering footprint
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 96 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller fig 39. lqfp64 soldering footprint sot314-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp64 package ax bx gx gy hy hx ay by p1 p2 d2 (8x) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 13.300 13.300 10.300 10.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 97 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 16. abbreviations 17. references [1] technical note adc design guidelines: https://www.nxp.com/docs/en/supporting-information/tn00009.pdf table 42. abbreviations acronym description ahb advanced high-performance bus apb advanced peripheral bus api application programming interface cdc communication device class dma direct memory access fro oscillator internal free-running oscillator , tuned to the factory specified frequency gpio general purpose input/output fro free running oscillator hid human interface device lsb least significant bit mcu microcontroller unit msc mass storage device pdm pulse density modulation pll phase-locked loop spi serial peripheral interface tcp/ip transmission control protocol/inter net protocol ttl transistor-transistor logic usart universal asynchronous receiver/transmitter
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 98 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 18. revision history table 43. revision history document id release date data sheet status change notice supersedes lpc5411x v.2.1 20180509 product data sheet - lpc5411x v.2.0 modifications: ? updated section 2 ? features and benefits ? : text for serial interfaces: usb 2.0 full-speed device controller with on-chip phy and dedicated dma controller supporting crystal-less operation in device mode using software library. see technical note tn00031 for more details. lpc5411x v.2.0 20180420 product data sheet - lpc5411x v.1.9 modifications: ? fixed figure 38 ?wlcsp49 soldering footprint?. ? added figure 39 ?lqfp64 soldering footprint?. lpc5411x v.1.9 20180126 product data sheet - lpc5411x v.1.8 modifications: ? updated a feature in section 7.19.5 ?spi serial i/o controller?: maxi mum data rate of 48 mbit/s in master mode and 15 mbit/s in slave mode for spi functions. was 71 mbit/s in master mode. ? updated section 11.10 ?spi interf aces?: the maximum supported bit rate for spi master mode is 48 mbit/s. was 71 mbit /s in master mode. lpc5411x v.1.8 20171102 product data sheet - lpc5411x v.1.7 modifications: ? updated broken cross references throughout the document. lpc5411x v.1.7 20170417 product data sheet - lpc5411x v.1.6 modifications: ? updated table 30 ?dynamic characteristics: i2s-bus interface pins [1][4]? ? updated table 16 ?static characteristics: power consumption in deep-sleep and deep power-down modes? and table 17 ?static characte ristics: power consumption in deep-sleep and deep power-down modes?: conditions for i dd supply current. lpc5411x v.1.6 20161222 product data sheet - lpc5411x v.1.5
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 99 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller modifications: ? updated section 2 ?features and benefits?: deleted text: real-time clock (rtc) running from the 32.768 khz clock from the list item: the micro-tick timer running from the watchdog oscillator can be used to wake-up the devi ce from any reduced power modes. see ? removed code executing in flash and sram from deep-sleep mode in table 23 ?dynamic characteristic: typical wake-up times from low power modes?. ? updated table 13 ?coremark score?: in arm co rtex-m4 in active mode; arm cortex-m0+ in sleep mode, changed cclk = 96 mhz; 5 system clock flash access time to cclk = 96 mhz; 6 system clock flash access time. in arm cortex-m 0+ in active mode; arm cortex-m4 in sleep mode, changed cclk = 96 mhz; 5 system clock fl ash access time to cclk = 96 mhz; 6 system clock flash access time. ? added text in section 2 ?features and benefits? and section 7.11 ?on-chip rom?: rom based usb drivers (hid, cdc, msc, dfu). ? replaced list item in rom api support in sectio n 2 ?features and benefits? and section 7.11 ?on-chip rom?: legacy, single, and dual image boot. ? changed text in clock generation in section 2 ?features and benefits?, section 7.18.3.1 ?features?, and section 7.21.1.2 ?watchdog o scillator (wdtosc)?: was, watchdog oscillator (wdtosc) with a frequency range of 200 khz to 1.5 mhz, now, watchdog oscillator (wdtosc) with a frequency range of 6khz to 1.5 mhz. ? updated table 28 ?dynamic characteristics: wa tchdog oscillator?. the min value of internal watchdog oscillator frequency is 6 khz. ? updated section 7.13.2 ?deep-sleep mode?. ? updated table 7 ?peripheral configuration in reduced power modes? and added table 8 ?wake-up sources for reduced power modes?. ? updated figure 32 ?power, clock, and debug connections?. ? updated figure 34 ?usb interface on a self-powered device where usb_vbus = 5 v? and figure 35 ?usb interface on a bus-powered device?. lpc5411x v.1.5 20160718 product data sheet - lpc5411x v.1.4 modifications: ? updated table 16 ?static characteristics: power consumption in deep-sleep and deep power-down modes?: idd typical values at deep-sleep mode, flash is powered down. table 43. revision history ?continued document id release date data sheet status change notice supersedes
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 100 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller lpc5411x v.1.4 20160711 product data sheet - lpc5411x v.1.3 modifications: ? updated table 16 ?static characteristics: power consumption in deep-sleep and deep power-down modes?. added max values to i dd supply current in deep-sleep mode and deep power-down mode. ? updated table 17 ?static characteristics: power consumption in deep-sleep and deep power-down modes?. added max values for deep-sleep mode and deep power-down mode. ? updated table 30 ?dynamic characterist ics: i2s-bus interface pins [1][4]?. ? updated table 31 ?spi dynamic characteristics[1]?. ? updated table 32 ?usart dynamic characteristics[1]?. ? updated table 5 ?termination of unused pins?. added usb_dp and usb_dm. ? updated usart features: maximum bit rates of 6.25 mbit/s in asynchronous mode and maximum data rate of 20 mbit/s in synchronous master mode and 16 mbit/s in synchronous slave mode.see section 7.17.4. ? added a remark to the features of sect ion 7.17.5 ?spi serial i/o controller?. ? updated spio features. added maximum and mini mum data rates for spi functions in master mode and slave mode. see section 7.17.5. ? updated figure 8 ?lpc5411x clock generation?. ? added a table note to table 16 ?static characte ristics: power consumption in deep-sleep and deep power-down modes?: [3] guaranteed by charac terization, not tested in production. vdd = 2.0 v. ? pll section renamed to system pll. see section 11.4 ?system pll?. ? added section 13.1 ?start-up behavior?. ? updated figure 31 ?standard i/o and reset pin configuration?. ? added section 13.6 ?suggested usb interface solutions?. ? added table 39 ?temperature sensor st atic and dynamic characteristics?. ? added figure 29 ?lls fit of the temperature sensor output voltage?. ? updated table 30 ?dynamic characteristics: i2s-bus interface pins [1][4]?: common to input and output, t wh and t wl typical values. ? added a remark to the features of section 7.17.8 ?i2s-bus interface?. ? updated table 19 ?typical ahb/apb peripheral power consumption [3][4][5]?: ? usb, gpio0, mailbox, sctimer/pwm, pint, rtc for: cpu: 12 mhz, sync apb bus: 12 mhz. ? gpio0 and gint for: cpu: 96mhz, sync apb bus: 96 mhz. ? gint for: cpu: 48 mhz, sync apb bus: 48 mhz. ? removed the section: po wer-up ramp conditions. ? updated table 25 ?dynamic characteristics of the pll[1]?: ? f ref changed to f in ; reference frequency to input frequency. ? removed f refjitter . ? updated table 30 ?dynamic characteristics: i2s-bus interface pins [1][4]? ? removed rise time (t r ) and fall time (t f ). table 43. revision history ?continued document id release date data sheet status change notice supersedes
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 101 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller lpc5411x v.1.3 20160325 product data sheet - lpc5411x v.1.2 modifications: ? updated figure 38 ?lqfp64 soldering footprint?. lpc5411x v.1.2 20160224 product data sheet - lpc5411x v.1.1 modifications: ? updated table 34 ?dynamic characteristics? on page 76: v dd = 1.62 v to 3.6 v and table note is: based on simulated values and for 2.7 v to 3.6 v. ? added figure 11 ?deep-sleep mode: typical suppl y current idd versus temperature for different supply voltages vdd? on page 53 and figure 12 ?deep power-down mode: typical supply current idd versus temperature for differ ent supply voltages vdd? on page 54. lpc5411x v.1.1 20160222 product data sheet - lpc5411x v.1 modifications: ? fixed graphic numbers. ? updated table 2 ?ordering options? on page 5. ? updated the list item in section 2 ?feature s and benefits?: rom-based usb drivers (hid, cdc, and msc). ? updated figure 6 ?lpc5411x memory mapping? on page 26 to include 128 kb on-chip flash and a note: the total size of flash and sram is part dependent. ? added section 7.21.1.4 ?rtc oscillator? on page 41. ? updated figure note of figure 9 ?typical coremark score? on page 49 to include ?all peripherals disabled.? ? added table description: t amb = ? 40 ? c to +105 ? c, unless otherwise specified.1.62 v ? v dd ? 3.6 v to table 15 ?static characteristics: power consumption in sleep mode? on page 51. ? moved figure 10 ?coremark power consumption: ty pical ma/mhz for m4 and m0+ cores? after table 15 ?static characteristics: power consumption in sleep mode? on page 51. ? updated table notes to table 18 ?typical peri pheral power consumption[1][2][3]? on page 54. ? added table 19 ?typical ahb/apb peripheral power consumption [3][4][5]? on page 54. ? removed table note: the values specified are simulated and absolute values, including package/bondwire capacitance from ?weak input pull-up/pull-down charac teristics? heading of table 20 ?static characteristics: pin characteristics? on page 56. ? renamed pll0 to pll. see table 24 ?pll lock times and current? on page 64. ? added table description: t amb = ? 40 ? c to +105 ? c. v dd = 1.62 v to 3.6 v to table 25 ?dynamic characteristics of the pll[1]? on page 65. ? changed the symbol in table 26 ?dynamic characteristic: fro? on page 65 to f osc(fro) . ? added table note: typical ratings are not guaran teed to table 30 ?dynamic characteristics: i2s-bus interface pins [1][4]?, table 31 ?spi dynam ic characteristics[1]? on page 71, and table 32 ?usart dynamic characteristics[1]? on page 74. ? updated footnote to: data based on characterizati on results, not tested in production. see table 26 ?dynamic characteristic: fro? on page 65. ? changed the order of the conditions for e d and e l(adj) in table 37 ?12-bit adc static characteristics? on page 79. lpc5411x v.1 20160216 product data sheet - - table 43. revision history ?continued document id release date data sheet status change notice supersedes
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 102 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. 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nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1][2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 103 of 105 nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc5411x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2018. all rights re served. product data sheet rev. 2.1 ? 9 may 2018 104 of 105 continued >> nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 5 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.1 termination of unused pins. . . . . . . . . . . . . . . 21 6.2.2 pin states in different power modes . . . . . . . . 21 7 functional description . . . . . . . . . . . . . . . . . . 22 7.1 architectural overview . . . . . . . . . . . . . . . . . . 22 7.2 arm cortex-m4 processor . . . . . . . . . . . . . . . 22 7.3 arm cortex-m4 integrat ed floating point unit (fpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 arm cortex-m0+ co-processor . . . . . . . . . . . 22 7.5 memory protection unit (mpu). . . . . . . . . . . . 22 7.6 nested vectored interr upt controller (nvic) for cortex-m4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 23 7.7 nested vectored interr upt controller (nvic) for cortex-m0+. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 23 7.8 system tick timer (systick) . . . . . . . . . . . . . . 24 7.9 on-chip static ram. . . . . . . . . . . . . . . . . . . . . 24 7.10 on-chip flash . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.11 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.12 memory mapping . . . . . . . . . . . . . . . . . . . . . . 25 7.13 system control . . . . . . . . . . . . . . . . . . . . . . . . 27 7.13.1 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.13.1.1 fro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.13.1.2 watchdog oscillator (wdtosc) . . . . . . . . . . . 27 7.13.1.3 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.13.1.4 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 28 7.13.1.5 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.13.2 clock generation . . . . . . . . . . . . . . . . . . . . . . 28 7.13.3 brownout detection . . . . . . . . . . . . . . . . . . . . . 30 7.13.4 safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.14 code security (code read protection - crp) 30 7.15 power control . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.15.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.15.2 deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 31 7.15.3 deep power-down mode . . . . . . . . . . . . . . . . 31 7.16 general purpose i/o (gpio) . . . . . . . . . . . . . 34 7.16.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.17 pin interrupt/pattern engine . . . . . . . . . . . . . . 34 7.17.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.18 ahb peripherals. . . . . . . . . . . . . . . . . . . . . . . 35 7.18.1 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 35 7.18.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.19 digital serial peripherals. . . . . . . . . . . . . . . . . 36 7.19.1 usb 2.0 device controller . . . . . . . . . . . . . . . 36 7.19.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.19.2 dmic subsystem . . . . . . . . . . . . . . . . . . . . . . 36 7.19.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.19.3 flexcomm interface serial communication. . . 37 7.19.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.19.4 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.19.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.19.5 spi serial i/o controller . . . . . . . . . . . . . . . . . 38 7.19.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.19.6 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . 38 7.19.7 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.19.8 i 2 s-bus interface . . . . . . . . . . . . . . . . . . . . . . 39 7.19.8.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.20 standard counter/timers (ctimer0 to 4). . . . . 40 7.20.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.20.2 sctimer/pwm subsystem . . . . . . . . . . . . . . . 40 7.20.2.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.20.3 windowed watchdog ti mer (wwdt) . . . . . . 42 7.20.3.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.20.4 rtc timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.20.4.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.20.5 multi-rate timer (mrt) . . . . . . . . . . . . . . . . . 43 7.20.5.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.20.6 micro-tick timer (utick) . . . . . . . . . . . . . . . . 44 7.20.6.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.21 12-bit analog-to-digital converter (adc). . . . 44 7.21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.22 temperature sensor . . . . . . . . . . . . . . . . . . . . 44 7.23 emulation and debugging . . . . . . . . . . . . . . . 45 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 46 9 thermal characteristics . . . . . . . . . . . . . . . . . 47 10 static characteristics . . . . . . . . . . . . . . . . . . . 48 10.1 general operating conditions . . . . . . . . . . . . . 48 10.2 coremark data . . . . . . . . . . . . . . . . . . . . . . . . 49 10.3 power consumption . . . . . . . . . . . . . . . . . . . . 51 10.4 pin characteristics . . . . . . . . . . . . . . . . . . . . . 57 10.4.1 electrical pin characteristics. . . . . . . . . . . . . . 60 11 dynamic characteristics. . . . . . . . . . . . . . . . . 63 11.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 63
nxp semiconductors lpc5411x 32-bit arm cortex-m4/m0+ microcontroller ? nxp semiconductors n.v. 2018. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 9 may 2018 document identifier: lpc5411x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 11.2 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.3 wake-up process . . . . . . . . . . . . . . . . . . . . . . 64 11.4 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.5 fro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.6 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.7 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 67 11.8 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.9 i 2 s-bus interface . . . . . . . . . . . . . . . . . . . . . . . 68 11.10 spi interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.11 usart interface. . . . . . . . . . . . . . . . . . . . . . . 75 11.12 sctimer/pwm output timing . . . . . . . . . . . . . 76 11.13 dmic subsystem . . . . . . . . . . . . . . . . . . . . . . 77 11.14 usb interface characteristics . . . . . . . . . . . . . 77 12 analog characteristics . . . . . . . . . . . . . . . . . . 79 12.1 bod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.2 12-bit adc characteristics . . . . . . . . . . . . . . . 80 12.2.1 adc input impedance. . . . . . . . . . . . . . . . . . . 83 12.3 temperature sensor . . . . . . . . . . . . . . . . . . . . 84 13 application information. . . . . . . . . . . . . . . . . . 86 13.1 start-up behavior . . . . . . . . . . . . . . . . . . . . . . 86 13.2 standard i/o pin configuration . . . . . . . . . . . . 86 13.3 connecting power, clocks, and debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.4 i/o power consumption. . . . . . . . . . . . . . . . . . 89 13.5 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 90 13.5.1 rtc printed circuit board (pcb) design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.6 suggested usb interface solutions . . . . . . . . 91 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 93 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 97 17 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . 98 19 legal information. . . . . . . . . . . . . . . . . . . . . . 102 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 102 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 103 20 contact information. . . . . . . . . . . . . . . . . . . . 103 21 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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